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d a t a sh eet product speci?cationsupersedes data of 2003 aug 07 2003 oct 01 integrated circuits SAA7824 cd audio decoder, digital servo and filterless dac with integrated pre-amp and laser control (phonic)
2003 oct 01 2 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control (phonic) SAA7824 contents 1 features 2 general description 3 ordering information 4 quick reference data 5 block diagram 6 pinning 7 functional description 7.1 data acquisition and hf data path 7.2 decoder part 7.2.1 principle operating modes of the decoder 7.2.2 decoder speed and crystal frequency 7.2.3 lock-to-disc mode 7.2.4 standby modes 7.3 crystal oscillator 7.4 data slicer and bit clock regenerator 7.5 dc offset cancellation 7.5.1 offset cancellation 7.5.2 reading back the dc offset value 7.6 demodulator 7.6.1 frame sync protection 7.6.2 efm demodulation 7.7 subcode data processing 7.7.1 q-channel processing 7.7.2 eiaj 3 and 4-wire subcode (cd graphics) interface 7.7.3 v4 subcode interface 7.7.4 cd text interface 7.8 fifo and error correction 7.8.1 flags output (cflg) 7.9 audio functions 7.9.1 de-emphasis and phase linearity 7.9.2 digital oversampling filter 7.9.3 concealment 7.9.4 mute, full-scale, attenuation and fade 7.9.5 peak detector 7.10 audio dac interface 7.10.1 internal dynamic element matching digital-to-analog converter 7.10.2 external dac interface 7.11 ebu interface 7.11.1 format 7.12 kill features 7.12.1 the kill circuit 7.12.2 silence injection 7.13 audio features off 7.14 the versatile pins interface 7.15 spindle motor control 7.15.1 motor output modes 7.15.2 spindle motor operating modes 7.15.3 loop characteristics 7.15.4 fifo overflow 7.16 servo part 7.16.1 diode signal processing 7.16.2 signal conditioning 7.16.3 focus servo system 7.16.4 radial servo system 7.16.5 off-track counting 7.16.6 track counting modes 7.16.7 defect detection 7.16.8 off-track detection 7.16.9 high-level features 7.16.10 driver interface 7.16.11 laser interface 7.17 microcontroller interface 7.17.1 microcontroller interface (4-wire bus mode) 7.17.2 microcontroller interface (i 2 c-bus mode) 7.17.3 decoder and shadow registers 7.17.4 summary of functions controlled by decoder registers 0 to f 7.17.5 summary of functions controlled by shadow registers 7.17.6 summary of servo commands 7.17.7 summary of servo command parameters 8 summary of servo command parameters values 9 limiting values 10 characteristics 11 operating characteristics (subcode interface timing) 12 operating characteristics (i 2 s-bus timing) 13 operating characteristics (microcontroller interface timing) 14 application information 15 package outline 16 soldering 16.1 introduction to soldering surface mount packages 16.2 reflow soldering 16.3 wave soldering 16.4 manual soldering 16.5 suitability of surface mount ic packages for wave and reflow soldering methods 17 data sheet status 18 definitions 19 disclaimers 20 purchase of philips i 2 c components
2003 oct 01 3 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 1 features decoder and servo parts are based upon the saa732x design (the original features are maintained) software compatibility is maintained with the saa732x by using a similar register structure (new features are controlled from new shadow registers) 1 , 2 and 4 speed lf (servo) signals converted to digital representations by 6 oversampling bitstream adcs hf part summed from signals d1 to d4 and converted into a digital signal by a data slicer on-chip buffering and filtering of the diode signals from the mechanism for signal optimization selectable dc offset cancellation of quiescent mechanism voltages and dark currents on-chip laser power control (up to 120 ma) laser on/off control, including soft start control (zero to nominal power in 1 ms) monitor control and feedback circuit to maintain nominal output power throughout laser life dynamic element matching dac with minimum external components dac performance of - 80 db total harmonic distortion + noise (thd + n) and 90 db signal-to-noise ratio (s/n) a-weighted separate left and right channel digital silence detection available on the kill pins digital silence detection on internal data and loopback (external) data 5 versatile pins, 2 inputs and 3 outputs integrated cd text decoder with separate microcontroller interface dedicated 4 mhz or 12 mhz clock output for microcontroller (configurable) configured for n-sub monitor diode on-chip clock multiplier allows the use of an 8.4672 mhz crystal or ceramic resonator the m1 version has an ebu mute function which allows independent muting of data being transmitted over the ebu interface whilst maintaining the spdif frame structure. 2 general description this document covers versions m0 and m1 of the cd audio decoder ic. the SAA7824 is a cd audio decoder ic which combines the function of the saa732x ic with the pre-amplifier and laser control functions previously found in the tza102x ic. the design is intended to reduce the external component count and hence the bill of material (bom). supply of this compact disc ic does not convey an implied license under any patent right to use this ic in any compact disc application.
2003 oct 01 4 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 3 ordering information 4 quick reference data type number package name description version SAA7824hl lqfp80 plastic low pro?le quad ?at package; 80 leads; body 12 12 1.4 mm sot315-1 symbol parameter conditions min. typ. max. unit v ddd digital supply voltage 1.65 1.8 1.95 v v dda analog supply voltage 3.0 3.3 3.6 v i dd(tot) total supply current n = 1 mode - 38 - ma n = 2 mode - 39 - ma n = 4 mode - 40 - ma f xtal crystal frequency - 8.4672 - mhz t amb ambient temperature 0 - 70 c t stg storage temperature - 55 - +125 c s/n dac onboard dac signal-to-noise ratio - 90 - db
2003 oct 01 5 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 5 block diagram handbook, full pagewidth dc offset compensation i ref scl sda rab sild v refo d1 9 6 v dda1 7 v dda2 16 8 52 54 55 76 77 78 79 19 18 49 50 36 37 38 59 58 60 56 51 40 71 72 73 74 75 34 35 33 28 31 30 32 29 21 24 25 26 23 22 27 42 43 44 46 47 48 45 62 39 68 67 15 66 65 64 80 57 53 10 11 12 13 14 3 4 2 1 d2 d3 d4 r1 r2 monitor adc monitor 5 v ssa1 17 v ssa2 20 v ssa3 sense lpower laser laser ra ef sclk wclk data moto1 moto2 cflag dobm fo sl cslice laser power control logic exfilter anti alias bias generator d1 to d4 sum high-pass filter control function output stages motor control error corrector ebu interface serial data interface bufinr bufinl bufoutr bufoutl mbl436 headphone buffers dacv pos dacrp dacrn daclp dacln dacv ref dacgnd dem dac scli wcli sdi serial data (loopback) interface flags data slicer and threshold control digital pll efm demodulator sram ram addresser subcode processor SAA7824 v1 v ssd1 41 70 v ddd2 61 v ssd2 63 v ddd1 v ddd3 69 v ssd3 v2 bufgnd bufv pos v3 v4 v5 lkill rkill audio processor peak detect kill versatile pins interface disc adc control part microcontroller interface test1 test2 test3 test4 test oscin oscout clk16 clk4/12 timing cdtrdy cdtdata cdtclk cd text interface sfsy status sbsy sub rck reset interface control decoder micro- controller interface voltage buffer hf and lf capture fig.1 block diagram.
2003 oct 01 6 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 6 pinning symbol pin i/o description lfpower 1 i laser power supply exfilter 2 o 10 nf capacitor for laser start-up control monitor 3 i laser monitor diode sense 4 i opu ground reference point for monitor measurement v ssa1 5 sup analog ground 1 i ref 6 o reference current output (24 k w resistor connected to analog ground) v dda1 7 sup analog supply voltage 1 v refo 8 i/o servo reference voltage d1 9 i diode voltage/current input (central diode signal input) d2 10 i diode voltage/current input (central diode signal input) d3 11 i diode voltage/current input (central diode signal input) d4 12 i diode voltage/current input (central diode signal input) r1 13 i diode voltage/current input (satellite diode signal input) r2 14 i diode voltage/current input (satellite diode signal input) cslice 15 i/o 10 nf capacitor for adaptive hf data slicer v dda2 16 sup analog supply voltage 2 v ssa2 17 sup analog ground 2 oscout 18 o crystal/resonator output oscin 19 i crystal/resonator input v ssa3 20 sup analog ground 3 dacgnd 21 i audio dac ground dacrp 22 o audio dac right channel differential positive output dacrn 23 o audio dac right channel differential negative output dacv ref 24 i/o audio dac decoupling point (10 m f or 100 nf to ground dacln 25 o audio dac left channel differential negative output daclp 26 o audio dac left channel differential positive output dacv pos 27 i audio dac positive supply voltage bufv pos 28 i audio buffer positive supply voltage bufinr 29 i audio buffer right input bufoutr 30 o audio buffer right output bufoutl 31 o audio buffer left output bufinl 32 i audio buffer left input bufgnd 33 i audio buffer ground lkill 34 o kill output for left channel (con?gurable as open-drain) rkill 35 o kill output for right channel (con?gurable as open-drain) cdtrdy 36 o cd text output to microcontroller ready ?ag cdtdata 37 o cd text output data to microcontroller cdtclk 38 i cd text microcontroller clock input cflag 39 o correction ?ag output (open-drain) v ssd1 40 sup digital ground 1
2003 oct 01 7 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 v ddd1 41 sup digital supply voltage 1 sdi 42 i serial data input (loopback) wcli 43 i word clock input (loopback) scli 44 i serial bit clock input (loopback) ef 45 o c2 error ?ag output data 46 o serial data output wclk 47 o word clock output sclk 48 o serial clock output clk16 49 o 16 mhz clock output clk4/12 50 o con?gurable 4 mhz or 12 mhz clock output reset 51 i power-on reset input (active low) sda 52 i/o microcontroller interface data input/output (open-drain) scl 53 i microcontroller interface clock input rab 54 i microcontroller interface r/w and load control input (4-wire) sild 55 i microcontroller interface r/w and load control input (4-wire) status 56 o servo interrupt request line/decoder status register/dc offset value readback output rck 57 i subcode clock input sub 58 o p to w subcode output sfsy 59 o subcode frame sync output sbsy 60 o subcode block sync output v ssd2 61 sup digital ground 2 dobm 62 o bi-phase mark output (externally buffered) v ddd2 63 sup digital supply voltage 2 ra 64 o radial actuator output fo 65 o focus actuator output sl 66 o sledge actuator output moto1 67 o motor output 1 output moto2 68 o motor output 2 output v ssd3 69 sup digital ground 3 v ddd3 70 sup digital supply voltage 3 v1 71 i versatile pin 1 input v2 72 i versatile pin 2 input v3 73 o versatile pin 3 output v4 74 o versatile pin 4 output v5 75 o versatile pin 5 output test1 76 i test pin 1 input test2 77 i test pin 2 input test3 78 i test pin 3 input test4 79 i test pin 4 input laser 80 o laser drive output symbol pin i/o description
2003 oct 01 8 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 handbook, full pagewidth SAA7824hl mbl437 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 laser test4 test3 test2 test1 v5 v4 v3 v2 v1 v ddd3 v ssd3 moto2 moto1 sl fo ra v ddd2 dobm v ssd2 dacgnd dacrp dacrn dacv ref dacln daclp dacv pos bufv pos bufinr bufoutr bufoutl bufinl bufgnd lkill rkill cdtrdy cdtdata cdtclk cflag v ssd1 lfpower exfilter monitor sense v ssa1 i ref v dda1 v refo d1 d2 d3 d4 r1 r2 cslice v dda2 v ssa2 oscout oscin v ssa3 sbsy sfsy sub rck status sild rab scl sda reset clk4/12 clk16 sclk wclk data ef scli wcli sdi v ddd1 fig.2 pin configuration.
2003 oct 01 9 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 7 functional description 7.1 data acquisition and hf data path the SAA7824 removes the need for an external diode signal pre-amplifier. a simplified diagram of the hf data path is illustrated in fig.3. the high-pass filter, equalizing filter hf gain and adaptive slicer are all register programmable, thus enabling the SAA7824 to be optimized for the intended application. handbook, full pagewidth mbl438 op-amp comp 67.7 mhz threshold control sliced data adaptive slicer op-amp op-amp bypass v ana summing amplifier equalising filter high-pass filter v ref d4_hf d1_hf hf_gain 5:0 d2_hf d3_hf fig.3 simplified block diagram of the hf data path and adaptive slicer. 7.2 decoder part 7.2.1 p rinciple operating modes of the decoder the decoding part supports a full audio specification and can operate at single-speed (n = 1), double-speed (n = 2) and quad-speed (n = 4). the factor n is called the overspeed factor. a simplified data flow through the decoder part is illustrated in fig.7 for the m0 version and fig.8 for the m1 version. 7.2.2 d ecoder speed and crystal frequency the SAA7824 is a 1 , 2 and 4 (three-speed) decoding device, with an internal phase-locked loop (pll) clock multiplier. table 1 gives the playback speeds that are achievable in conjunction with crystal frequency, mechanism, and internal clock settings (selectable via decoder register b). 7.2.3 l ock - to - disc mode for electronic shock absorption applications, the SAA7824 can be put into lock-to-disc mode. this allows constant angular velocity (cav) disc playback with varying input data rates from the inside-to-outside of the disc. in the lock-to-disc mode, the fifo is blocked and the decoder will adjust its output data rate to the disc speed. hence, the frequency of the i 2 s-bus (wclk and sclk) clocks are dependent on the disc speed. in the lock-to-disc mode there is a limit on the maximum variation in disc speed that the SAA7824 will follow. disc speeds must always be within 25% to 100% range of their nominal value. the lock-to-disc mode is enabled or disabled by decoder register e.
2003 oct 01 10 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 7.2.4 s tandby modes the SAA7824 may be placed in two standby modes, selected by decoder register b (it should be noted that the device core is still active): standby 1: cd stop mode; most i/o functions are switched off standby 2: cd pause mode; audio output features are switched off, but the motor loop, the motor output and the subcode interfaces remain active; this is also called a hot pause. in the standby modes the various pins will have the following values: moto1 and moto2: put in to high-impedance, pwm mode (standby 1 and reset: operating in standby 2); put in high-impedance, pdm mode (standby 1 and reset: operating in standby 2) pins scl and sda: no interaction; normal operation continues pins sclk, wclk, data, ef and dobm: 3-state in both standby modes; normal operation continues after reset pins oscin, oscout, clk16 and clk4/12: no interaction; normal operation continues pins v1 to v5 and cflag: no interaction; normal operation continues. table 1 playback speeds 7.3 crystal oscillator the crystal oscillator is a conventional 2-pin design which can also operate with ceramic resonators. the external components used around the crystal are illustrated in fig.4 together with component values (c1 and c2) for a given crystal type given in table 2. oscillator frequencies that is used with the SAA7824 is 8.4672 mhz. register b register e f xtal = 8.4672 mhz 0xxx 0xxx n = 1 1xxx 0xxx n = 2; voltage mode only 0xxx 1xxx n = 4; voltage mode only handbook, halfpage SAA7824 oscillator xtal oscout oscin c2 c1 mbl439 fig.4 crystal configuration. table 2 external capacitor selection based upon the crystal type crystal load capacitance (c l ) maximum series crystal resistance (r s ) external load capacitors 8 mhz c1 c2 10 pf <300 w 8pf 8pf 20 pf <300 w 27 pf 27 pf 30 pf <300 w 47 pf 47 pf
2003 oct 01 11 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 7.4 data slicer and bit clock regenerator the SAA7824 has an integrated adaptive data slicer which is clocked at 67 mhz. the slice level is controlled by internal current sources which are switched onto and integrated by the external capacitor connected to the cslice pin. the currents are switched under the control of a digital phase-locked loop (dpll). regeneration of the bit clock is achieved with an internal fully digital pll. no external components are required and the bit clock is not output. the pll has two registers (8 and 9) for selecting bandwidth and equalization. the pll loop response is illustrated in fig.5. for certain applications an off-track input is necessary. this is internally connected from the servo part (its polarity can be changed by the foc_parm1 parameter), but may be input via pin v1 if selected by register c. if this flag is high, the SAA7824 will assume that its servo part is following the wrong track, and will flag all incoming hf data as incorrect. 7.5 dc offset cancellation unwanted dc offsets can exist within the photo-diode signals and are defined as the dc present in the system when the laser diode is switched off. they arise from various sources of imperfection within the system such as leakage in the photo diodes and offsets in the optical pick-up (opu) circuitry. the SAA7824 is capable of measuring these offsets and minimizing them. 7.5.1 o ffset cancellation a number of registers are associated with the dc offset cancellation function; these registers are given in table 3. the measurement time of the dc offset is regulated by new shadow register c (bank 2). a longer time will yield more accurate results but will result in greater measurement durations. new shadow register 3 (bank 3) is used to select which diode is to be measured. 7.5.2 r eading back the dc offset value the microcontroller needs to be able to read the dc offset measurements in order to calculate the correct cancellation value [for writing back to new shadow register 7 (bank 3)]. this is achieved by using the status pin and setting decoder register 7 to xx10. shadow register c (bank 3) can then be used to control the status pin output; the register settings are given in table 20. once the measurement time has been set and the diode selected, the status pin should be set to read the dc offset ready flag [new shadow register c (bank 3) = x01x]. this signal will toggle high after the prescribed measurement time. changing the diode selection will result in the measurement timer being automatically reset. the microcontroller can read back the measurement by setting the status pin to output the dc offset value [new shadow register c (bank 3) = x10x]. the offset value is repeatedly streamed out through the status pin and is uart compatible. it should be noted that the msb is inverted and will require re-inverting after the offset value has been captured. timing information for this signal is illustrated in fig.6. the final dc cancellation value (as calculated by the microcontroller) can then be written to new shadow register 7 (bank 3). this is a multiple write register containing the cancellation values for all six diodes. mgs178 handbook, halfpage f 3 . pll, lpf 2 . pll bandwidth 1 . pll integrator pll loop response fig.5 digital pll loop response. points 1, 2 and 3 are all programmable via decoder register 8.
2003 oct 01 12 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 table 3 registers relating to the dc offset cancellation shaden bits shadow register address data function initial 10 (bank 2) c dc offset measurement times 1100 xx00 settling time = 354 m s reset xx01 settling time = 1 ms - xx10 settling time = 2 ms - xx11 settling time = 10 ms - 11 (bank 3) 3 diode selection for dc offset measurement 0011 0000 select d1 reset 0001 select d1 - 0010 select d2 - 0011 select d3 - 0100 select d4 - 0101 select r1 - 0110 select r2 - 0111 select d1 - c status pin control 1100 x00x status pin outputs decoder status register information reset x01x status pin outputs dc offset ready ?ag - x10x status pin outputs dc offset value - 7 dc cancellation levels 0111 multi-write (9 4 bits) dc cancellation values for diodes d1 to d4 and r1 and r2; see table 20 - handbook, full pagewidth mbl440 d7 d6 d5 d4 d3 d2 d1 d0 d0 d1 272.1/n m s 2.19/n m s fig.6 serial data format for dc offset data.
2003 oct 01 13 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... handbook, full pagewidth subcode processor digital pll and demodulator fifo error corrector fade/mute/ interpolate digital filter phase compensation de-emphasis filter internal kill 1 0 1 0 1 0 1 0 1 0 i 2 s/eiaj bus interface i 2 s/eiaj loopback interface wcli scli sdi dacrp daclp dacrn dacln sclk wclk data ef decoder register 3 decoder register c decoder register 3 register f decoder register a 1 0 1 0 1: decoder register 3 1 101x 0: decoder register 3 = 101x (cd-rom modes) 0: new shadow register a bank 2 = 0xxx 1: new shadow register a bank 2 = 1xxx 1: shadow register 7 = xx1x 0: shadow register 7 = xx0x 1: shadow register 7 = xx1x 0: shadow register 7 = xx0x 0: register d = xx01 1: decoder register a = xx0x 0: decoder register a 1 xx1x v4 subcode interface microcontroller interface cd graphics interface cd text interface ebu interface sbsy sfsy sub rck dobm v4 sda output from data slicer 1: decoder register 3 = xx10 (1f s mode) 0: decoder register 3 1 xx10 1: no pre-emphasis detected or register d = 01xx (de-emphasis signal at v5) 0: pre-emphasis detected and register d 1 01xx lkill rkill loopback kill mgs180 1 0 onboard dac cdtrdy cdtclk cdtdata new shadow register 7 bank 2: 0xxx = pass all data 1xxx = pass correct data only 1 0 fig.7 simplified data flow of decoder functions for the m0 version.
2003 oct 01 14 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... handbook, full pagewidth subcode processor digital pll and demodulator fifo error corrector fade/mute/ interpolate digital filter phase compensation de-emphasis filter internal kill 1 0 1 0 1 0 1 0 1 0 i 2 s/eiaj bus interface i 2 s/eiaj loopback interface wcli scli sdi dacrp daclp dacrn dacln sclk wclk data ef decoder register 3 decoder register c decoder register 3 register f decoder register a 1 0 0 1 1: decoder register 3 1 101x 0: decoder register 3 = 101x (cd-rom modes) 0: new shadow register a bank 2 = 0xx 1: new shadow register a bank 2 = 1xxx 1: shadow register 7 = xx1x 0: shadow register 7 = xx0x 1: shadow register 7 = xx1x 0: shadow register 7 = xx0x 0: register d = xx01 1: decoder register a = xx0x 0: decoder register a = xx1x activate mute (decoder reg 0) mute bypass (shadow register 7 bank 1) hard mute (decoder reg c) v4 subcode interface microcontroller interface cd graphics interface cd text interface ebu interface ebu mute sbsy sfsy sub rck dobm v4 sda output from data slicer 1: decoder register 3 = xx10 (1f s mode) 0: decoder register 3 1 xx10 1: no pre-emphasis detected or register d = 01xx (de-emphasis signal at v5) 0: pre-emphasis detected and register d 1 01xx lkill rkill loopback kill mdb501 1 0 onboard dac cdtrdy cdtclk cdtdata new shadow register 7 bank 2: 0xxx = pass all data 1xxx = pass correct data only 1 0 fig.8 simplified data flow of decoder functions for the m1 version.
2003 oct 01 15 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 7.6 demodulator 7.6.1 f rame sync protection a double timing system is used to protect the demodulator from erroneous sync patterns in the serial data. the master counter is only reset if: a sync coincidence is detected; sync pattern occurs 588 1 efm clocks after the previous sync pattern a new sync pattern is detected within 6 efm clocks of its expected position. the sync coincidence signal is also used to generate the pll lock signal, which is active high after 1 sync coincidence is found, and reset low if during 61 consecutive frames no sync coincidence is found. the pll lock signal can be accessed via the sda or status pins selected by decoder registers 2, 7 and new shadow register c (bank 3). also incorporated in the demodulator is a run length 2 (rl2) correction circuit. every symbol detected as rl2 will be pushed back to rl3. to do this, the phase error of both edges of the rl2 symbol are compared and the correction is executed at the side with the highest error probability. 7.6.2 efm demodulation the 14-bit efm data and subcode words are decoded into 8-bit symbols. 7.7 subcode data processing 7.7.1 q- channel processing the 96-bit q-channel word is accumulated in an internal buffer. the last 16 bits are used internally to perform a cyclic redundancy check (crc). if the data is good, the subqready-i signal will go low. subqready-i can be read via the sda or status pins, selected via decoder registers 2, 7 and new shadow register c (bank 3). good q-channel data may be read from pin sda. 7.7.2 eiaj 3 and 4- wire subcode (cd graphics ) interface data from all the subcode channels (p-to-w) may be read via the subcode interface, which conforms to eiaj cp-2401. the interface is enabled and configured as either a 3 or 4-wire interface via decoder register f. the subcode interface output formats are illustrated in fig.9, where the rck signal is supplied by another device such as a cd graphics decoder. 7.7.3 v4 subcode interface data of subcode channels, q-to-w, may be read via pin v4 if selected via decoder register d. the format is similar to rs232 and is illustrated in fig.10. the subcode sync word is formed by a pause of (200/n) m s minimum. each subcode byte starts with a logic 1 followed by 7 bits (q-to-w). the gap between bytes is variable between (11.3/n) m s and (90/n) m s. the subcode data is also available in the ebu output (dobm) in a similar format. 7.7.4 cd text interface r-to-w subcode data is captured and stored until a complete cd text pack is formed. the least significant 16 bits of the pack are used for a crc. the behaviour of the cd text interface is controlled by new shadow register 7 (bank 2). the interface can either flag all data (i.e. passed or failed crc) or it can flag good data only. the data ready flag is monitored via pin cdtrdy and is active low. the pulse width varies from 73/n m s, for the first three packs, to 317/n m s for the fourth pack. when a pack becomes available, the initial value of the cdtdata pin indicates the crc result (high = passed; low = failed). the microcontroller can fetch the data by applying a clock signal (maximum frequency = 5 mhz) to pin cdtclk and reading the subsequent bitstream on pin cdtdata. the 128 data bits are streamed out lsb first. a complete cd text pack consists of 4 header bytes, 12 data bytes, and 2 crc bytes although the latter 2 bytes are dropped internally once the crc calculation is complete. please refer to the red book for further details relating to the format of a cd text pack the timing diagram for the cd text interface is illustrated in fig.11.
2003 oct 01 16 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 handbook, full pagewidth sbsy sfsy rck sub sfsy rck sub sfsy rck sub eiaj 4-wire subcode interface eiaj 3-wire subcode interface sf0 sf1 sf2 sf3 sf97 sf0 sf1 p-w p-w p-w p-w p-w p-w pqrstuvw mbg410 sf0 sf1 sf2 sf3 sf97 sf0 sf1 fig.9 eiaj subcode (cd graphics) interface format.
2003 oct 01 17 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 w96 1qrstuvw 1q 200/n m s min 11.3/n m s 11.3/n m s min 90/n m s max mbg401 fig.10 subcode format and timing on pin v4. where n = disc speed. handbook, full pagewidth crc flag d0 d1 d2 d3 d126 d127 cdtclk cdtrdy cdtdata mbl441 73/n m s to 317/n m s ~1/n ns 200 ns (min) fig.11 cd text interface format and timing. where n = disc speed. 7.8 fifo and error correction the SAA7824 has a 8 frame fifo. the error corrector is a t = 2, e = 4 type, with error corrections on both c1 (32 symbol) and c2 (28 symbol) frames. four symbols are used from each frame as parity symbols. this error corrector can correct up to two errors on the c1 level and up to four errors on the c2 level. the error corrector also contains a flag processor. flags are assigned to symbols when the error corrector cannot ascertain if the symbols are definitely good. c1 generates output flags which are read after de-interleaving by c2, to help in the generation of c2 output flags. the c2 output flags are used by the interpolator for concealment of uncorrectable errors. they are also output via the ebu signal (dobm). the ef output will flag bytes in error in both audio and cd-rom modes. 7.8.1 f lags output (cflg) the flags output pin cflg shows the status of the error corrector and interpolator and is updated every frame (7.35 n khz). in the SAA7824, 8 1-bit flags are present on the cflg pin as illustrated in fig.12. this signal shows the status of the error corrector and interpolator. the first flag bit, f1, is the absolute time sync signal, the fifo-passed subcode sync and relates the position of the subcode sync to the audio data (dac output). this flag may also be used in a super fifo or in the synchronization of different players. the output flags can be made available at bit 4 of the ebu data format (lsb of the 24-bit data word), if selected by decoder register a.
2003 oct 01 18 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 handbook, full pagewidth f1 f2 f3 f4 f5 f6 f7 f8 f1 f8 11.3/n m s 33.9/n m s 33.9/n m s mbg425 fig.12 flag output timing diagram. where n = disc speed. table 4 output ?ags f1 f2 f3 f4 f5 f6 f7 f8 description 0xxxxxxxno absolute time sync 1xxxxxxx absolute time sync x0 0xxxxxc1fr ame contained no errors x0 1xxxxxc1fr ame contained 1 error x1 0xxxxxc1fr ame contained 2 errors x1 1xxxxxc1fr ame uncorrectable x x x 0 0 x x 0 c2 frame contained no errors x x x 0 0 x x 1 c2 frame contained 1 error x x x 0 1 x x 0 c2 frame contained 2 errors x x x 0 1 x x 1 c2 frame contained 3 errors x x x 1 0 x x 0 c2 frame contained 4 errors x x x 1 1 x x 1 c2 frame uncorrectable xxxxx0 0xno interpolations xxxxx0 1xat least one 1-sample interpolation xxxxx1 0xat least one hold and no interpolations xxxxx1 1xat least one hold and one 1-sample interpolation
2003 oct 01 19 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 7.9 audio functions 7.9.1 d e - emphasis and phase linearity when pre-emphasis is detected in the q-channel subcode, the digital filter automatically includes a de-emphasis filter section. when de-emphasis is not required, a phase compensation filter section controls the phase of the digital oversampling filter to 1 within the band 0 to 16 khz. with de-emphasis the filter is not phase linear. if the de-emphasis signal is set to be available at pin v5, selected via decoder register d, then the de-emphasis filter is bypassed. 7.9.2 d igital oversampling filter for optimizing performance with an external dac, the SAA7824 contains a 2 to 4 times oversampling iir filter. the filter specification of the 4 times oversampling filter is given in table 5. these attenuations do not include the sample-and-hold at the external dac output or the dac post filter. when using the oversampling filter, the output level is scaled - 0.5 db down to avoid overflow on full-scale sine wave inputs (0 to 20 khz). table 5 filter speci?cation 7.9.3 c oncealment a 1-sample linear interpolator becomes active if a single sample is flagged as erroneous but cannot be corrected. the erroneous sample is replaced by a level midway between the preceding and following samples. left and right channels have independent interpolators. if more than one consecutive non-correctable sample is found, the last good sample is held. a 1-sample linear interpolation is then performed before the next good sample; see fig.13. in cd-rom modes (i.e. the external dac interface is selected to be in a cd-rom format) concealment is not executed. 7.9.4 m ute , full - scale , attenuation and fade a digital level controller is present on the SAA7824 which performs the functions of soft mute, full-scale, attenuation and fade; these are selected via decoder register 0: mute: signal reduced to 0 in a maximum of 128 steps; 3/n ms attenuation: signal scaled by - 12 db full-scale: ramp signal back to 0 db level; from mute it takes 3/n ms fade: activates a 128 stage counter which allows the signal to be scaled up or down in 0.07 db steps C 128 = full-scale C 120 = - 0.5 db (i.e. full-scale if oversampling filter is used) C32= - 12 db C 0 = mute. 7.9.5 p eak detector the peak detector measures the highest audio level (absolute value) on positive peaks for left and right channels. the 8 most significant bits are output in the q-channel data in place of the crc bits. bits 81 to 88 contain the left peak value (bit 88 = msb) and bits 89 to 96 contain the right peak value (bit 96 = msb). the values are reset after reading q-channel data via pin sda. pass band stop band attenuation 0 to 9 khz - 0.001 db 19 to 20 khz - 0.03 db - 24 khz 3 25 db - 24 to 27 khz 3 38 db - 27 to 35 khz 3 40 db - 35 to 64 khz 3 50 db - 64 to 68 khz 3 31 db - 68 khz 3 35 db - 69 to 88 khz 3 40 db
2003 oct 01 20 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 interpolation hold interpolation mga372 ok error ok error error error ok ok fig.13 concealment mechanism. 7.10 audio dac interface 7.10.1 i nternal dynamic element matching digital - to - analog converter the onboard audio dem dac operates at an oversampling rate of 96f s and is designed for operation with an audio input at 1f s . the dac is equipped with two pairs of stereo outputs for driving medium impedance line outputs and for directly driving low impedance headphones. a pair of analog inputs are provided to enable external audio sources to make use of the headphone output buffers. audio data from the decoder part of the SAA7824 can be routed as described in sections 7.10.1.1 and 7.10.1.2. table 6 shadow register 7.10.1.1 use of internal dac setting shadow register 7 to 0010 will route audio data from the decoder into the internal dac. to enable the on-board dac, the dac interface format (set by register 3) must be set to 16-bit 1f s mode, either i 2 s-bus or eiaj format. cd-rom mode can also be used if interpolation is not required. the serial data output pins for interfacing with an external dac (sclk, wclk, data and ef) are set to high-impedance. shaden bits shadow register address data function reset 01 (bank 1) 7 control of onboard dac 0111 0000 use external dac or route audio data back into onboard dac (loopback mode) reset 0010 route audio data directly into onboard dac (non-loopback mode) -
2003 oct 01 21 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 7.10.1.2 loopback external data into onboard dac the onboard dac can also be set to accept serial data inputs from an external source, e.g. an electronic shock absorption (esa) ic. this is known as loopback mode and is enabled by setting shadow register 7 to 0000. this enables the serial data output pins (sclk, wclk, data and ef) so that data can be routed from the SAA7824 to an external esa system (or external dac). the serial data from an external esa ic can then also be input to the onboard dac on the SAA7824 by utilising the serial data input interface (scli, sdi and wcli). in this mode, a wide range of data formats to the external esa ic can be programmed as shown in table 7. however, the serial input on the SAA7824 will always expect the input data from the esa ic to be 16-bit 1f s and the same data format, either i 2 s-bus or eiaj, as the serial output format (set by decoder register 3). 7.10.2 e xternal dac interface audio data from the SAA7824 can be sent to an external dac, identical to the saa732x series, in loopback mode (i.e. shadow register 7 is set to 0000). the SAA7824 is compatible with a wide range of external dacs. eleven formats are supported and are given in table 7. figures 14 and 15 show the philips i 2 s-bus and the eiaj data formats respectively. when the decoder is operated in lock-to-disc mode, the sclk frequency is dependent on the disc speed factor d. all formats are msb first and 1f s is 44.1 khz. the polarity of the wclk and the data can be inverted; selectable by decoder register 7. it should be noted that ef is only a defined output in cd-rom and 1f s modes. when using an external dac (or when using the onboard dac in non-loopback mode), the serial data inputs to the onboard dac (scli, sdi and wcli) should be tied to ground. table 7 dac interface formats note 1. in this mode the first 16 bits contain data, but if any of the fade, attenuate or de-emphasis filter functions are activated then the first 18 bits contain data. register 3 sample frequency number of bits sclk (mhz) format interpolation 1010 f s 16 2.1168 n cd-rom (i 2 s-bus) no 1011 f s 16 2.1168 n cd-rom (eiaj) no 1110 f s 16/18 (1) 2.1168 n philips i 2 s-bus 16/18 bits (1) yes 0010 f s 16 2.1168 n eiaj 16 bits yes 0110 f s 18 2.1168 n eiaj 18 bits yes 0000 4f s 16 8.4672 n eiaj 16 bits yes 0100 4f s 18 8.4672 n eiaj 18 bits yes 1100 4f s 18 8.4672 n philips i 2 s-bus 18 bits yes 0011 2f s 16 4.2336 n eiaj 16 bits yes 0111 2f s 18 4.2336 n eiaj 18 bits yes 1111 2f s 18 4.2336 n philips i 2 s-bus 18 bits yes
2003 oct 01 22 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... left channel data (wclk normal polarity) sclk 15 14 15 14 10 data wclk lsb error flag msb error flag lsb error flag msb error flag ef (cd-rom and 1f s modes only) 0 1 mbg424 fig.14 philips i 2 s-bus data format (16-bit word length). sclk 17 17 0 data wclk 0 left channel data msb error flag lsb error flag msb error flag mbg423 ef (cd-rom and 1f s modes only) fig.15 eiaj data format (18-bit word length).
2003 oct 01 23 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 7.11 ebu interface the bi-phase mark digital output signal at pin dobm is in accordance with the format defined by the iec 60958 specification. three different modes can be selected via decoder register a: dobm pin held low data taken before concealment, mute and fade (must always be used for cd-rom modes) data taken after concealment, mute and fade. an additional mute function is available via shadow register 7 (bank 1) and decoder register 0 and c. they provide the following: hard mute: immediate mute of the audio sample in the rom mode at 1 , 2 or 4 soft mute: 3 ms ramp up or ramp down of the audio samples in the 1 audio mode bypass: switches the ebu mute function out of the ebu signal path. 7.11.1 f ormat the digital audio output consists of 32-bit words (subframes) transmitted in bi-phase mark code (two transitions for a logic 1 and one transition for a logic 0). words are transmitted in blocks of 384. the ebu frame format is given in table 8. table 8 ebu frame format; see also table 9 table 9 description of ebu frame function function bits description sync 0 to 3 - auxiliary 4 to 7 not used; normally zero error ?ags 4 cflg error and interpolation ?ags when selected by register a audio sample 8 to 27 ?rst 4 bits not used (always zero); twos complement; lsb = bit 12, msb = bit 27 validity ?ag 28 valid = logic 0 user data 29 used for subcode data (q-to-w) channel status 30 control bits and category code function description sync the sync word is formed by violation of the bi-phase rule and therefore does not contain any data. its length is equivalent to 4 data bits. the 3 different sync patterns indicate the following situations: sync b; start of a block (384 words), word contains left sample; sync m; word contains left sample (no block start) and sync w; word contains right sample. audio sample left and right samples are transmitted alternately. validity ?ag audio samples are ?agged (bit 28 = 1) if an error has been detected but was uncorrectable. this ?ag remains the same even if data is taken after concealment. user data subcode bits q-to-w from the subcode section are transmitted via the user data bit. this data is asynchronous with the block rate. channel status the channel status bit is the same for left and right words. therefore a block of 384 words contains 192 channel status bits. the category code is always cd. the bit assignment is given in table 10.
2003 oct 01 24 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 table 10 bit assignment function bits description control 0 to 3 copy of crc checked q-channel control bits 0 to 3; bit 2 is logic 1 when copy permitted; bit 3 is logic 1 when recording has pre-emphasis reserved mode 4 to 7 always zero category code 8 to 15 cd: bi t 8 = logic 1, all other bits = logic 0 clock accuracy 28 to 29 set by register a; 10 = level i; 00 = level ii; 01 = level iii remaining 6 to 27 and 30 to 191 always zero 7.12 kill features 7.12.1 t he kill circuit the kill circuit detects digital silence by testing for an all-zero or all-ones data word in the left and right channels. this occurs in two places; prior to the digital filter (internal kill), and in the digital dac (loopback/external kill). programming bit 3 of new shadow register a (bank 2) determines whether internal or external data is used. the output is switched to active high when silence has been detected for at least 270 ms, or if mute is active, or in cd-rom mode. two kill modes are available which can be selected by decoder register c: mono kill: lkill and rkill are both active high when silence is detected on left and right channels simultaneously stereo kill: lkill and rkill are active high independently of each other when silence is detected on either channel. 7.12.2 s ilence injection the silence inject function monitors the left and right kill signals and forces the analog dac into silence when kill is asserted. this improves the internal signal-to-noise ratio (snr) by preventing any spurious noise from reaching the dac. the silence inject function can be enabled or disabled by programming bit 2 of the new shadow register a (bank 2). 7.13 audio features off the audio features can be turned off (selected by decoder register e) and will affect the following functions: digital filter, fade, peak detector, internal kill circuit (although rkill and lkill outputs still active) are disabled v5 (if selected to be the de-emphasis flag output) and the ebu outputs become undefined. the ebu output should be set low prior to switching the audio features off and after switching the audio features back on, a full-scale command should be given. 7.14 the versatile pins interface the SAA7824 has five pins that can be reconfigured for different applications. the functions of these versatile pins are identical to the saa732x series and can be programmed by decoder registers c, d and shadow register 3 (bank 1) as shown in table 11.
2003 oct 01 25 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 table 11 pin applications pin name pin number type register address register data function v1 71 input 1100 xxx1 external off-track signal input - xxx0 internal off-track signal used input may be read via decoder status bit; selected via register 2 v2 72 input -- input may be read via decoder status bit; selected via register 2 v3 73 output 1100 00xx output = 0 - 01xx output = 1 v4 74 output 1101 0000 4-line motor drive (using v4 and v5) - xx01 q-to-w subcode output - xx10 output = 0 - xx11 output = 1 v5 75 output 1101 01xx de-emphasis output (active high) - 10xx output = 0 - 11xx output = 1 7.15 spindle motor control 7.15.1 m otor output modes the spindle motor speed is controlled by a fully integrated digital servo. address information from the internal 8 frame fifo and disc speed information are used to calculate the motor control output signals. several output modes, selected by decoder register 6, are supported: pulse density, 2-line (true complement output), (1 n) mhz sample frequency pwm output, 2-line, (22.05 n) khz modulation frequency pwm output, 4-line, (22.05 n) khz modulation frequency cdv motor mode. 7.15.1.1 pulse density output mode in the pulse density mode the motor output pin (moto1) is the pulse density modulated motor output signal. a 50% duty factor corresponds with the motor not actuated, higher duty factors mean acceleration, lower duty factors means braking. in this mode, the moto2 signal is the inverse of the moto1 signal. both signals change state only on the edges of a (1 n) mhz internal clock signal. 7.15.1.2 pwm output mode (2-line) in the pwm mode the motor acceleration signal is put in pulse-width modulation form on the moto1 output. the motor braking signal is pulse-width modulated on the moto2 output. the timing is illustrated in fig 16. a typical application diagram is illustrated in fig 17. rep t = 45 m s t 240 ns dead accelerate brake moto1 moto2 mga366 fig.16 2-line pwm mode timing.
2003 oct 01 26 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 mga365 - 2 v ss + m moto1 moto2 10 w 100 nf fig.17 motor 2-line pwm mode application diagram. 7.15.1.3 pwm output mode (4-line) using two extra outputs from the versatile pins interface, it is possible to use the SAA7824 with a 4-input motor bridge. the timing is illustrated in fig 18. a typical application diagram is illustrated in fig 19. moto1 moto2 v4 v5 rep t = 45 m s t 240 ns dead ovl t = 240 ns accelerate brake mga367 - 1 fig.18 4-line pwm mode timing.
2003 oct 01 27 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 mga364 - 2 v ss + m moto1 v4 moto2 v5 100 nf 10 w fig.19 motor 4-line pwm mode application diagram. 7.15.1.4 cdv/cav output mode in the cdv motor mode, the fifo position will be put in pulse-width modulated form on the moto1 pin [carrier frequency (300 d) hz], where d is the disc speed factor. the pll frequency signal will be put in pulse-density modulated form (carrier frequency 4.23 n mhz) on the moto2 pin. the integrated motor servo is disabled in this mode. the pwm signal on moto1 corresponds to a total memory space of 20 frames, therefore the nominal fifo position (half full) will result in a pwm output of 60%. in the lock-to-disc (cav) mode the cdv motor mode is the only mode that can be used to control the motor. 7.15.2 s pindle motor operating modes the operating modes of the motor servo are controlled by decoder register 1; see table 12. in the SAA7824 decoder there is an anti-windup mode for the motor servo, selected via decoder register 1. when the anti-windup mode is activated the motor servo integrator will hold if the motor output saturates. 7.15.2.1 motor ov ?ag the SAA7824 contains a servo loop that is used to regulate the spindle speed. the motor ov flag is provided to indicate when the motor output has overloaded. during a large change in disc speed i.e. by a long jump or x-factor change, the motor ov flag will be asserted due to the full and longer duration required to attain the new desired speed. the ov flag indicates when the internal processes of the modulator have overflowed and not necessarily when the output power has reached 100%. similarly, the flag does not fall at a specific output power level but at a specific speed error level. the error level at which the flag falls is determined by the selected servo gain, and will be internally equivalent to +3 gain or - 3 gain. 7.15.2.2 power limit in start mode 1, start mode 2, stop mode 1 and stop mode 2, a fixed positive or negative voltage is applied to the motor. this voltage can be programmed as a percentage of the maximum possible voltage, via register 6, to limit current drain during start and stop. the following power limits are possible: 100% (no power limit), 75%, 50% or 37% of maximum.
2003 oct 01 28 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 7.15.3 l oop characteristics the gain and crossover frequencies of the motor control loop can be programmed via decoder registers 4 and 5. the following parameter values are possible: gains: 3.2, 4.0, 6.4, 8.0, 12.8, 16, 25.6 and 32 crossover frequency f 4 : 0.5 n hz, 0.7 n hz, 1.4 n hz and 2.8 nhz crossover frequency f 3 : 0.85 n hz, 1.71 n hz and 3.42 n hz. it should be noted that the crossover frequencies f 3 and f 4 are scaled with the overspeed factor n whereas the gains are not. 7.15.4 fifo overflow if fifo overflow occurs during play mode (e.g. as a result of motor rotational shock), the fifo will be automatically reset to 50% and the audio interpolator will conceal as much as possible to minimize the effect of data loss. table 12 operating modes mode description start mode 1 the disc is accelerated by applying a positive voltage to the spindle motor. no decisions are involved and the pll is reset. no disc speed information is available for the microcontroller. start mode 2 the disc is accelerated as in start mode 1, however the pll will monitor the disc speed. when the disc reaches 75% of its nominal speed, the controller will switch to jump mode. the motor status signals selectable via register 2 are valid. jump mode motor servo enabled but fifo kept reset at 50%, integrator is held. the audio is muted but it is possible to read the subcode. it should be noted that in the cd-rom modes the data, on ebu and the i 2 s-bus, is not muted. jump mode 1 similar to jump mode but motor integrator is kept at zero. it is used for long jumps where there is a large change in disc speed. play mode fifo released after resetting to 50% and the audio mute is released. stop mode 1 disc is braked by applying a negative voltage to the motor; no decisions are involved. stop mode 2 the disc is braked as in stop mode 1 but the pll will monitor the disc speed. as soon as the disc reaches 12% (or 6%, depending on the programmed brake percentage, via register e) of its nominal speed, the motstop status signal will go high and switch the motor servo to off mode. off mode motor not steered. mga362 - 2 g f 4 fbw 3 f fig.20 motor servo mode diagram.
2003 oct 01 29 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 7.16 servo part 7.16.1 d iode signal processing the photo detector in conventional two-stage three-beam compact disc systems normally contains six discrete diodes. four of these diodes (three for single foucault systems) carry the central aperture signal (ca) while the other two diodes (satellite diodes) carry the radial tracking information. the ca signals are summed into an hf signal for the decoder function and are also differentiated (after analog-to-digital conversion) to produce the low frequency focus control signals. the low frequency content of the six (five if single foucault) photo diode inputs are converted to digital pulse density modulated (pdm) bitstreams by six sigma-delta adcs. these support a range of opus by interfacing to voltage mode mechanisms and by having 16 selectable gain ranges in two sets, one set for d1-to-d4 and the other for r1 and r2. table 13 shadow register settings to control diode voltage ranges shaden bits shadow register address data voltage (mv) initial 01 (bank 1) a signal magnitude control for diodes d1 to d4 (lf only) 1010 0000 20 - 0001 25 - 0010 30 - 0011 40 - 0100 60 - 0101 75 - 0110 100 - 0111 120 - 1000 150 - 1001 200 - 1010 270 - 1011 350 - 1100 450 - 1101 600 - 1110 720 - 1111 960 reset
2003 oct 01 30 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 01 (bank 1) c signal magnitude control for diodes r1 and r2 (lf only) 1100 0000 20 - 0001 25 - 0010 30 - 0011 40 - 0100 60 - 0101 75 - 0110 100 - 0111 120 - 1000 150 - 1001 200 - 1010 270 - 1011 350 - 1100 450 - 1101 600 - 1110 720 - 1111 960 reset shaden bits shadow register address data voltage (mv) initial 7.16.2 s ignal conditioning the digital codes retrieved from the adcs are applied to logic circuitry to obtain the various control signals. the signals from the central aperture diodes are processed to obtain a normalised focus error signal: where the detector set-up is assumed to be as shown in fig.21. in the event of single foucault focusing method, the signal conditioning can be switched under software control such that the signal processing is as follows: the error signal, fe n , is further processed by a proportional integral and differential (pid) filter section. a focus ok (fok) flag is generated by the central aperture signal and an adjustable reference level. this signal is used to provide extra protection for the track-loss (tl) generation, the focus start-up procedure and the dropout detection. the radial or tracking error signal is generated by the satellite detector signals r1 and r2. the radial error signal can be formulated as follows: re s = (r1 - r2) re_gain + (r1 + r2) re_offset. where the index s indicates the automatic scaling operation which is performed on the radial error signal. this scaling is necessary to avoid non-optimum dynamic range usage in the digital representation and reduces the radial bandwidth spread. furthermore, the radial error signal will be made free from offset during start-up of the disc. the four signals from the central aperture detectors, together with the satellite detector signals generate a track position signal (tpi) which can be formulated as follows: tpi = sign [(d1 + d2 + d3 + d4) - (r1 + r2) sum_gain] where the weighting factor sum_gain is generated internally by the SAA7824 during initialization. fe n d1 d2 C d1 d2 + ---------------------- d3 d4 C d3 d4 + ---------------------- C = fe n 2 d1 d2 C d1 d2 + ---------------------- =
2003 oct 01 31 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 handbook, full pagewidth d3 d1 d2 satellite diode r1 satellite diode r2 d1 d3 d2 d4 satellite diode r1 satellite diode r2 d1 d2 d3 d4 satellite diode r1 satellite diode r2 single foucault astigmatic focus double foucault mbg422 fig.21 detector arrangement. 7.16.3 f ocus servo system 7.16.3.1 focus start-up five initially loaded coefficients influence the start-up behaviour of the focus controller. the automatically generated triangular voltage can be influenced by 3 parameters; for height (ramp_height) and dc offset (ramp_offset) of the triangle and its steepness (ramp_incr). for protection against false focus point detections two parameters are available which are an absolute level on the ca signal (ca_start) and a level on the fe n signal (fe_start). when this ca level is reached the fok signal becomes true. if the fok signal is true and the level on the fe n signal is reached, the focus pid is enabled to switch-on when the next zero crossing is detected in the fe n signal. 7.16.3.2 focus position control loop the focus control loop contains a digital pid controller which has 5 parameters that are available to the user. these coefficients influence the integrating (foc_int), proportional (foc_lead_length, part of foc_parm3) and differentiating (foc_pole_lead, part of foc_parm1) action of the pid and a digital low-pass filter (foc_pole_noise, part of foc_parm2) following the pid. the fifth coefficient foc_gain influences the loop gain. 7.16.3.3 dropout detection this detector can be influenced by one parameter (ca_drop). the fok signal will become false and the integrator of the pid will hold if the ca signal drops below this programmable absolute ca level. when the fok signal becomes false it is assumed, initially, to be caused by a black dot. 7.16.3.4 focus loss detection and fast restart whenever fok is false for longer than approximately 3 ms, it is assumed that the focus point is lost. a fast restart procedure is initiated which is capable of restarting the focus loop within 200 to 300 ms depending on the programmed coefficients of the microcontroller.
2003 oct 01 32 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 7.16.3.5 focus loop gain switching the gain of the focus control loop (foc_gain) can be multiplied by a factor of 2 or divided by a factor of 2 during normal operation. the integrator value of the pid is corrected accordingly. the differentiating (foc_pole_lead) action of the pid can be switched at the same time as the gain switching is performed. 7.16.3.6 focus automatic gain control loop the loop gain of the focus control loop can be corrected automatically to eliminate tolerances in the focus loop. this gain control injects a signal into the loop which is used to correct the loop gain. since this decreases the optimum performance, the gain control should only be activated for a short time (for example, when starting a new disc). 7.16.4 r adial servo system 7.16.4.1 level initialization during start-up an automatic adjustment procedure is activated to set the values of the radial error gain (re_gain), offset (re_offset) and satellite sum gain (sum_gain) for tpi level generation. the initialization procedure runs in a radial open loop situation and is 300 ms. this start-up time period may coincide with the last part of the motor start-up time period: automatic gain adjustment: as a result of this initialization the amplitude of the re signal is adjusted to within 10% around the nominal re amplitude offset adjustment: the additional offset in re due to the limited accuracy of the start-up procedure is less than 50 nm tpi level generation: the accuracy of the initialization procedure is such that the duty factor range of tpi becomes 0.4 < duty factor < 0.6 (default duty factor = tpi high/tpi period). 7.16.4.2 sledge control the microcontroller can move the sledge in both directions via the steer sledge command. 7.16.4.3 tracking control the actuator is controlled using a pid loop filter with user defined coefficients and gain. for stable operation between the tracks, the s-curve is extended over 75% of the track. on request from the microcontroller, s-curve extension over 2.25 tracks is used, automatically changing to access control when exceeding those 2.25 tracks. both modes of s-curve extension make use of a track-count mechanism. in this mode, track counting results in an automatic return-to-zero track, to avoid major disturbances in the audio output and providing improved shock resistance. the sledge is continuously controlled, or provided with step pulses to reduce power consumption using the filtered value of the radial pid output. alternatively, the microcontroller can read the average voltage on the radial actuator and provide the sledge with step pulses to reduce power consumption. filter coefficients of the continuous sledge control can be preset by the user. 7.16.4.4 access the access procedure is divided into two different modes (see table 14), depending on the requested jump size. table 14 access modes note 1. the microcontroller can be preset. the access procedure makes use of a track counting mechanism, a velocity signal based on a fixed number of tracks passed within a fixed time interval, a velocity set point calculated from the number of tracks to go and a user programmable parameter indicating the maximum sledge performance. if the number of tracks remaining is greater than the brake_distance then the sledge jump mode should be activated or, the actuator jump should be performed. the requested jump size together with the required sledge breaking distance at maximum access speed defines the brake_distance value. during the actuator jump mode, velocity control with a pi controller is used for the actuator. the sledge is then continuously controlled using the filtered value of the radial pid output. all filter parameters (for actuator and sledge) are user programmable. access type jump size (1) access speed actuator jump 1 - brake_distance decreasing velocity sledge jump brake_distance - 32768 maximum power to sledge (1)
2003 oct 01 33 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 in the sledge jump mode maximum power (user programmable) is applied to the sledge in the correct direction while the actuator becomes idle (the content of the actuator integrator leaks to zero just after the sledge jump mode is initiated). the actuator can be electronically damped during sledge jump. the gain of the damping loop is controlled via the hold_mult parameter. the fast track jumping circuitry can be enabled or disabled via the xtra_preset parameter. 7.16.4.5 radial automatic gain control loop the loop gain of the radial control loop can be corrected automatically to eliminate tolerances in the radial loop. this gain control injects a signal into the loop which is used to correct the loop gain. since this decreases the optimum performance, the gain control should only be activated for a short time (for example, when starting a new disc). this gain control differs from the level initialization. the level initialization should be performed first. the disadvantage of using the level initialization without the gain control is that only tolerances from the front-end are reduced. 7.16.5 o ff - track counting the track position signal (tpi) is a flag which is used to indicate whether the radial spot is positioned on the track, with a margin of 0.25 of the track pitch. in combination with the radial polarity flag (rp) the relative spot position over the tracks can be determined. these signals can have uncertainties caused by: disc defects such as scratches and fingerprints the hf information on the disc, which is considered as noise by the detector signals. in order to determine the spot position with sufficient accuracy, extra conditions are necessary to generate a track loss signal (tl) and an off-track counter value. these extra conditions influence the maximum speed and this implies that, internally, one of the following three counting states is selected: 1. protected state: used in normal play situations. a good protection against false detection caused by disc defects is important in this state. 2. slow counting state: used in low velocity track jump situations. in this state a fast response is important rather than the protection against disc defects (if the phase relationship between tl and rp of 0.5 p radians is affected too much, the direction cannot then be determined accurately). 3. fast counting state: used in high velocity track jump situations. highest obtainable velocity is the most important feature in this state. 7.16.6 t rack counting modes fast counting mode is auto-selected for a track crossing speed above 1200 tracks/s. in this case the off-track counting decrements occur only for effect of the rp signal, and the direction of the jump is already known because the slow counting mode occurs before going into fast counting mode. when the slow counting mode is selected, the maximum track crossing speed that can be reached is 12 khz (providing that the maximum value for rad_pole_lead is used). in this case the direction of the jump is given by the phase shift between rp and tl (+90 degrees for outward jumps, - 90 degrees for inward jumps). the number of pulses in the tl signal gives the number of tracks crossed. when the fast counting mode is enabled, whenever the track crossing speed goes below 12 khz, the counting mode is automatically changed to slow. 7.16.7 d efect detection a defect detection circuit is incorporated into the SAA7824. if a defect is detected, the radial and focus error signals may be zeroed, resulting in better playability. the defect detector can be switched off, applied only to focus control or applied to both focus and radial controls under software control (part of foc_parm1). the defect detector (see fig 22) has programmable set points selectable by the parameter defect_parm. 7.16.8 o ff - track detection during active radial tracking, off-track detection has been realised by continuously monitoring the off-track counter value. the off-track flag becomes valid whenever the off-track counter value is not equal to zero. depending on the type of extended s-curve, the off-track counter is reset after 0.75 extend or at the original track in the 2.25 track extend mode.
2003 oct 01 34 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 handbook, full pagewidth decimation filter fast filter defect generation programmable hold-off slow filter defect output sat1 sat2 + - mbg421 fig.22 block diagram of the defect detector. 7.16.9 h igh - level features 7.16.9.1 interrupt mechanism and status pin the status pin is an output which can be configured by decoder register 7 and new shadow register c (bank 3) for one of three different modes of operation. these are: output the interrupt signal generated by the servo part (it should be noted that the selection of this mode will override all other modes) output the decoder status bit (active low) selected by decoder register 2 (only available in 4-wire bus mode) output dc offset information (it should be noted that this mode is used in conjunction with the decoder status mode; see section 7.5). eight signals from the interrupt status register are selectable from the servo part via the interrupt_mask parameter. the interrupt is reset by sending the read high-level status command. the 8 signals are as follows: focus lost: dropout of longer than 3 ms subcode ready subcode absolute seconds changed subcode discontinuity detected: new subcode time before previous subcode time, or more than 10 frames later than previous subcode time radial error: during radial on-track, no new subcode frame occurs within the time defined by the playwatchtime parameter; during radial jump, less than 4 tracks have been crossed during the time defined by the jumpwatchtime parameter autosequencer state change autosequencer error subcode interface blocked: the internal decoder interface is being used. it should be noted that if the status pin is configured to output decoder status information [decoder register 7 = xx10 and new shadow register c (bank 3) = x00x] and either the microcontroller writes a different value to decoder register 2 or the decoder interface is enabled then the status output will change. 7.16.9.2 decoder interface the decoder interface allows decoder and shadow registers to be programmed and subcode q-channel data to be read via servo commands. the interface is enabled or disabled by the preset latch command (and the xtra_preset parameter). 7.16.9.3 automatic error handling three watchdogs are present: focus: detects focus dropout of longer than 3 ms, sets focus lost interrupt, switches off radial and sledge servos and disables the drive-to-disc motor radial play: started when radial servo is in on-track mode and a first subcode frame is found; detects when the maximum time between two subcode frames exceeds the time set by the playwatchtime parameter; it then sets the radial error interrupt, switches radial and sledge servos off and puts the disc motor into jump mode radial jump: active when radial servo is in long jump or short jump modes; detects when the off-track counter value decreases by less than 4 tracks between two readings (the time interval is set by the jumpwatchtime parameter); it then sets the radial jump error, switches radial and sledge servos off to cancel jump. the focus watchdog is always active, the radial watchdogs are selectable via the radcontrol parameter.
2003 oct 01 35 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 7.16.9.4 automatic sequencers and timer interrupts two automatic sequencers are implemented (and must be initialized after power-on): auto-start sequencer: controls the start-up of focus, radial and motor auto-stop sequencer: brakes the disc and shuts down the servos. when the automatic sequencers are not used it is possible to generate timer interrupts, defined by the time_parameter coefficient. 7.16.9.5 high-level status the read high-level status command can be used to obtain the interrupt, decoder, autosequencer status registers and the motor start time. use of the read high-level status command clears the interrupt status register, and re-enables the subcode read via a servo command. 7.16.10 d river interface the control signals (pins ra, fo and sl) for the mechanism actuators are pulse density modulated. the modulating frequency can be set to either 1.0584 or 2.1168 mhz; controlled via the xtra_preset parameter. an analog representation of the output signals can be achieved by connecting a 1st-order low-pass filter to the outputs. during reset (i.e. reset pin is held low) the ra, fo and sl pins are high-impedance. at all other times, when the laser is switched off, the ra and fo pins output a 2 mhz 50% duty factor signal. 7.16.11 l aser interface the laser diode pre-amplifier function is built into the SAA7824 and is illustrated in fig.24. the current can be regulated, up to 120 ma in four steps ranging from 58% up to full power. new shadow register a (bank 2) and new shadow register 3 (bank 3) are used to select the step values. the voltage derived from the monitor diode is maintained at a steady state by the laser drive circuitry, regulating the current through the laser diode. the type of monitor diode being used (150 mv or 180 mv) must be selected by new shadow register 7 (bank 2) (reset state = 150 mv). the laser can be switched on or off by the xtra_preset parameter; it is automatically driven if the focus control loop is active.
2003 oct 01 36 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 7.17 microcontroller interface communication on the microcontroller interface can be set-up in three different modes: 4-wire bus mode: where: C scl = serial clock C sda = serial data C rab=r/ w control and data strobe (active high) for writing to decoder registers 0 to f, reading status bit selected via decoder register 2 and reading q-channel subcode C sild = r/w control and data strobe (active low) for servo commands 3-wire bus mode: where: C scl = serial clock C sda = serial data C rab = not used, pulled low C sild = r/w control and data strobe (active low) for servo commands i 2 c-bus mode: i 2 c-bus protocol where the SAA7824 behaves as slave device, activated by setting rab = high and sild = low where: Ci 2 c-bus slave address (write mode) = 30h C i 2 c-bus slave address (read mode) = 31h C maximum data transfer rate = 400 kbits/s. it should be noted that when using the i 2 c-bus mode, only servo commands can be used. therefore, writing to decoder registers 0 to f, reading decoder status and reading q-channel subcode data must be performed by servo commands. the 3-wire mode is very similar to the 4-wire mode, except that all communication to the decoder is via the servo. communication to the servo uses the same hardware protocol and timing as the 4-wire mode. extra servo commands exist for read and write access to the decoder via the internal decoder interface. the internal interface must be enabled by using the xtra_preset command. rab is not used and must be tied low; see fig.23 handbook, halfpage mdb502 microcontroller interface (decoder) microcontroller interface SAA7824 rab = low sda scl sild fig.23 microcontroller interface for the 3-wire mode.
2003 oct 01 37 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 handbook, full pagewidth mbl442 monitor laser power control [register a (bank 2) and register 3 (bank 3)] mech_sel laser diode 47 nf monitor diode exfilter laser error amplifier floating reference power amplifier power-down or laser off g m v dda g m v sense fig.24 simplified block diagram of the laser driver.
2003 oct 01 38 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 7.17.1 m icrocontroller interface (4- wire bus mode ) 7.17.1.1 writing data to registers 0 to f the sixteen 4-bit programmable configuration registers, 0 to f (see table 15), can be written to via the microcontroller interface using the protocol shown in fig.25. it should be noted that sild must be held high; a3 to a0 identifies the register number and d3 to d0 is the data. the data is latched into the register on the low-to-high transition of rab. 7.17.1.2 writing repeated data to registers 0 to f the same data can be repeated several times (e.g. for a fade function) by applying extra rab pulses as shown in fig.26. it should be noted that scl must stay high between rab pulses. 7.17.1.3 multiple writes to the new shadow registers some of the new shadow registers are a multiple of four bits in length and require a number of write operations to fill them up; see section 7.17.5. they must be completely filled before writing to another register, otherwise unpredictable behaviour may result. the protocol for writing to these registers is exactly the same as the decoder registers; see fig.25. the write command must be executed multiple times with the same address content. the first four bits of data in a sequence of write commands represent the most significant nibble of the register, while the last four represent the least significant nibble. the data content can change from one write to the next without consequence. 7.17.1.4 reading decoder status information on sda there are several internal status signals, selected via register 2, which can be made available on the sda line: subqready-i: low if new subcode word is ready in q-channel register motstart1: high if motor is turning at 75% or more of nominal speed motstart2: high if motor is turning at 50% or more of nominal speed motstop: high if motor is turning at 12% or less of nominal speed; can be set to indicate 6% or less (instead of 12% or less) via register e pll lock: high if sync coincidence signals are found v1: follows input on pin v1 v2: follows input on pin v2 motor-ov: high if the motor servo output stage saturates. the status read protocol is illustrated in fig.27. it should be noted that sild must be held high. 7.17.1.5 reading q-channel subcode to read the q-channel subcode direct in the 4-wire bus mode, the subqready-i signal should be selected as the status signal. the subcode read protocol is illustrated in fig.28. it should be noted that sild must be held high; after subcode read starts, the microcontroller may take as long as it wants to terminate the read operation. when enough subcode has been read (1 to 96 bits), the reading can be terminated by pulling rab low. alternatively, the q-channel subcode can be read using a servo command as follows: use the read high-level status command to monitor the subcode ready signal send the read subcode command and read the required number of bytes (up to 12) send the read high-level status command; to re-enable the decoder interface. 7.17.1.6 behaviour of the subqready-i signal when the crc of the q-channel word is good, and no subcode is being read, the subqready-i status signal will react as illustrated in fig.29. when the crc is good and the subcode is being read, the timing in fig.30 applies. if t 1 (subqready-i status low to end of subcode read) is below 2.6/n ms, then t 2 = 13.1/n ms (i.e. the microcontroller can read all subcode frames if it completes the read operation within 2.6/n ms after the subcode is ready). if these criteria are not met, it is only possible to guarantee that t 3 will be below 26.2/n ms (approximately). if subcode frames with failed crcs are present, the t 2 and t 3 times will be increased by 13.1/n ms for each defective subcode frame. it should be noted that in the lock-to-disc mode n is replaced by d, which is the disc speed factor.
2003 oct 01 39 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 7.17.1.7 write servo commands a write data command is used to transfer data (a number of bytes) from the microcontroller, using the protocol illustrated in fig.31. the first of these bytes is the command byte and the following are data bytes; the number (between 1 and 7) depends on the command byte. it should be noted that rab must be held low; the command or data is interpreted by the SAA7824 after the high-to-low transition of sild; there must be a minimum time of 70 m s between sild pulses. 7.17.1.8 writing repeated data in servo commands the same data byte can be repeated by applying extra sild pulses as illustrated in fig.32. scl must be high between the sild pulses. 7.17.1.9 read servo commands a read data command is used to transfer data (status information) to the microcontroller, using the protocol shown in fig.33. the first byte written determines the type of command. after this byte a variable number of bytes can be read. it should be noted that rab must be held low; after the end of the command byte (low-to-high transition on sild) there must be a delay of 70 m s before data can be read (i.e. the next high-to-low transition on sild) and there must be a minimum time of 70 m s between sild pulses. 7.17.2 m icrocontroller interface (i 2 c- bus mode ) bytes are transferred over the interface in groups (i.e. servo commands) of which there are two types: write data commands and read data commands. the sequence for a write data command (that requires 3 data bytes) is as follows: 1. send start condition. 2. send address 30h (write). 3. write command byte. 4. write data byte 1. 5. write data byte 2. 6. write data byte 3. 7. send stop condition. it should be noted that more than one command can be sent in one write sequence. the sequence for a read data command (that reads 2 data bytes) is as follows: 1. send start condition. 2. send address 30h (write). 3. write command byte. 4. send stop condition. 5. send start condition. 6. send address 31h (read). 7. read data byte 1. 8. read data byte 2. 9. send stop condition. it should be noted that the timing constraints specified for the read and write servo commands must still be adhered to. handbook, full pagewidth a3 a2 a1 a0 d3 d2 d1 d0 sda (saa782x) scl (microcontroller) rab (microcontroller) sda (microcontroller) mbl445 high-impedance fig.25 microcontroller write protocol for registers 0 to f.
2003 oct 01 40 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 handbook, full pagewidth a3 a2 a1 a0 d3 d2 d1 d0 sda (saa782x) mbl446 scl (microcontroller) rab (microcontroller) sda (microcontroller) high-impedance fig.26 microcontroller write protocol for registers 0 to f (repeat mode). handbook, full pagewidth sda (saa782x) mbl443 status scl (microcontroller) rab (microcontroller) sda (microcontroller) high-impedance fig.27 microcontroller read protocol for decoder status on sda. handbook, full pagewidth q1 q2 q3 qn? sda (saa782x) mbl444 qn? qn status crc ok scl (microcontroller) rab (microcontroller) fig.28 microcontroller protocol for reading q-channel subcode.
2003 oct 01 41 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 handbook, full pagewidth sda (saa782x) 10.8/n ms 15.4/n ms 2.3/n ms read start allowed high impedance crc ok crc ok mbl447 scl (microcontroller) rab (microcontroller) fig.29 subqready-i status timing when no subcode is read. handbook, full pagewidth q1 q2 q3 qn sda (saa782x) t 1 t 2 t 3 mbl448 scl (microcontroller) rab (microcontroller) fig.30 subqready-i status timing when subcode is read.
2003 oct 01 42 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 handbook, full pagewidth d7 d6 d5 d4 d3 d2 d1 d0 sda (saa782x) sild (microcontroller) scl (microcontroller) sda (microcontroller) sild (microcontroller) sda (microcontroller) command data1 data2 data3 command or data byte high-impedance microcontroller write (one byte: command or data) microcontroller write (full command) mbl449 fig.31 microcontroller protocol for write servo commands. handbook, full pagewidth sild (microcontroller) sda (microcontroller) microcontroller write (full command) command data1 mbg413 fig.32 microcontroller protocol for repeated data in write servo commands.
2003 oct 01 43 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 handbook, full pagewidth data1 data2 data3 command sild (microcontroller) sild (microcontroller) scl (microcontroller) sda (microcontroller) sd (saa782x) sd (saa782x) d7 d6 d5 d4 d3 d2 d1 d0 data byte microcontroller read (one data byte) microcontroller read (full command) mbl450 fig.33 microcontroller protocol for read servo commands. 7.17.3 d ecoder and shadow registers to maintain compatibility with the saa732x series, decoder registers 0 to f and the shadow registers are largely unchanged. however, to control the extra functionality of SAA7824, the shadow registers have been extended to include new shadow registers. all shadow registers are accessed by using the two lsbs (bits 0 and 1) of decoder register f. these bits are called shaden1 and shaden2 respectively. these bits are decoded according to table 15. this two bit encoding allows the use of three shadow register banks; bank 1 (saa732x shadow registers), and banks 2 and 3 (new shadow registers). only the four addresses 3, 7, a and c are implemented in any one bank. any other addresses sent while accessing any of the shadow register banks are invalid and have no effect. when shaden1 and shaden2 are both set to logic 0 (decoder register f set to xx00) all subsequent addresses are decoded by the main decoder registers again. access to decoder register f is always enabled so that shaden1 and shaden2 can be set or reset as required. the shaden bits and subsequent shadow registers are programmed identically to the main decoder registers, i.e. they can be directly programmed when using the SAA7824 in 4-wire mode or programmed via the servo interface when using 3-wire or i 2 c-bus modes. the main decoder registers are given in table 16 and the shadow registers in table 18. details of the new shadow registers can be found in tables 19 to 22.
2003 oct 01 44 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 table 15 shadow register accessibility 7.17.4 s ummary of functions controlled by decoder registers 0 to f table 16 registers 0 to f shaden2 shaden1 function initial 0 0 access decoder registers 0 to f reset 0 1 access saa732x shadow registers (bank 1) - 1 0 access new shadow registers (bank 2) - 1 1 access new shadow registers (bank 3) - register address data function initial (1) 0 (fade and attenuation) 0000 x000 mute reset x010 attenuate - x001 full-scale - x100 step-down - x101 step-up - 0 ebu mute (for m1 version only) 0xxx ebu mute inactive reset 1xxx ebu mute active - 1 (motor mode) 0001 x000 motor off mode reset x001 motor stop mode 1 - x010 motor stop mode 2 - x011 motor start mode 1 - x100 motor start mode 2 - x101 motor jump mode - x111 motor play mode - x110 motor jump mode 1 - 1xxx anti-windup active - 0xxx anti-windup off reset 2 (status control) 0010 0000 status = subqready-i reset 0001 status = motstart1 - 0010 status = motstart2 - 0011 status = motstop - 0100 status = pll lock - 0101 status = v1 - 0110 status = v2 - 0111 status = motor-ov - unavailable via the i 2 c-bus or 3-wire mode 1000 status = fifo over?ow - 1001 status = shock detect - 1010 status = latched shock detect - 1011 status = latched shock detect reset -
2003 oct 01 45 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 3 (dac output) 0011 1010 i 2 s-bus; cd-rom mode - 1011 eiaj; cd-rom mode - 1100 i 2 s-bus; 18-bit; 4f s mode reset 1111 i 2 s-bus; 18-bit; 2f s mode - 1110 i 2 s-bus; 16-bit; f s mode - 0000 eiaj; 16-bit; 4f s - 0011 eiaj; 16-bit; 2f s - 0010 eiaj; 16-bit; f s - 0100 eiaj; 18-bit; 4f s - 0111 eiaj; 18-bit; 2f s - 0110 eiaj; 18-bit; f s - 4 (motor gain) 0100 0000 motor gain g = 3.2 reset 0001 motor gain g = 4.0 - 0010 motor gain g = 6.4 - 0011 motor gain g = 8.0 - 0100 motor gain g = 12.8 - 0101 motor gain g = 16.0 - 0110 motor gain g = 25.6 - 0111 motor gain g = 32.0 - 5 (motor bandwidth) 0101 xx00 motor f 4 = 0.5 n hz reset xx01 motor f 4 = 0.7 nhz - xx10 motor f 4 = 1.4 nhz - xx11 motor f 4 = 2.8 nhz - 00xx motor f 3 = 0.85 n hz reset 01xx motor f 3 = 1.71 nhz - 10xx motor f 3 = 3.42 nhz - 6 (motor output con?guration) 0110 xx00 motor power maximum 37% reset xx01 motor power maximum 50% - xx10 motor power maximum 75% - xx11 motor power maximum 100% - 00xx moto1, moto2 pins 3-state reset 01xx motor pwm mode - 10xx motor pdm mode - 11xx motor cdv mode - register address data function initial (1)
2003 oct 01 46 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 7 (dac output and status pin control) 0111 xx00 interrupt signal from servo only at status pin reset xx10 status bit from decoder status register or dc offset information at status pin [see also new shadow register c (bank 3)] - x0xx dac data normal value reset x1xx dac data inverted value - 0xxx left channel ?rst at dac (wclk normal) reset 1xxx right channel ?rst at dac (wclk inverted) - 8 (pll loop ?lter bandwidth) see table 16 - 9 (pll equalization) 1001 0011 pll loop ?lter equalization reset 0001 pll 30 ns over-equalization - 0010 pll 15 ns over-equalization - 0100 pll 15 ns under-equalization - 0101 pll 30 ns under-equalization - a (ebu output) 1010 xx0x ebu data before concealment - xx1x ebu data after concealment and fade reset x0x0 level ii clock accuracy (<1000 ppm) reset x0x1 level i clock accuracy (<50 ppm) - x1x0 level iii clock accuracy (>1000 ppm) - x1x1 ebu off - output low - 0xxx ?ags in ebu off reset 1xxx ?ags in ebu on - b (speed control) 1011 x000 standby 1: cd-stop mode reset x010 standby 2: cd-pause mode - x011 operating mode - 00xx single-speed mode reset 10xx double-speed mode - c (versatile pins interface and kill function) 1100 xxx1 external off-track signal input at v1 - xxx0 internal off-track signal used (v1 may be read via status) reset xx0x stereo kill - xx1x mono kill reset 00xx v3 = 0 reset 01xx v3 = 1 - ebu mute mode (for m1 version only) 0xxx mute type = soft mute audio; only available at 1 speed reset 1xxx mute type = rom hard mute; available at 1 , 2 and 4 speed - register address data function initial (1)
2003 oct 01 47 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 note 1. the initial column shows the power-on reset state. d (versatile pins interface) 1101 0000 4-line motor (using v4 and v5) - xx01 q-to-w subcode at v4 - xx10 v4 = 0 - xx11 v4 = 1 reset 01xx de-emphasis signal at v5, no internal de-emphasis ?lter - 10xx v5 = 0 - 11xx v5 = 1 reset e 1110 xxx0 motor brakes to 12% reset xxx1 motor brakes to 6% - xx0x lock-to-disc mode disabled reset xx1x lock-to-disc mode enabled - x0xx audio features disabled - x1xx audio features enabled reset 0xxx quad-speed mode disabled reset 1xxx quad-speed mode enabled - f (subcode interface and shadow register enable) 1111 x0xx subcode interface off reset x1xx subcode interface on - 0xxx 4-wire subcode reset 1xxx 3-wire subcode - xx00 shaden bits = 00; shadow registers not enabled; addresses will be decoded by main decoder registers reset xx01 shaden bits = 01; saa732x shadow registers (bank 1) enabled; all subsequent addresses will be decoded by shadow register (bank 1), not decoder registers - xx10 shaden bits = 10; new shadow registers (bank 2) enabled; all subsequent addresses will be decoded by shadow register (bank 2) - xx11 shaden bits = 11; new shadow registers (bank 3) enabled; all subsequent addresses will be decoded by shadow register (bank 3) - register address data function initial (1)
2003 oct 01 48 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 table 17 loop ?lter bandwidth note 1. the initial column shows the power-on reset state. 7.17.5 s ummary of functions controlled by shadow registers table 18 bank 1 shadow register settings (single write) register address data function initial (1) loop bandwidth (hz) internal bandwidth (hz) low-pass bandwidth (hz) 8 (pll loop ?lter bandwidth) 1000 0000 1640 n 525 n 8400 n - 0001 3279 n 263 n 16800 n - 0010 6560 n 131 n 33600 n - 0100 1640 n 1050 n 8400 n - 0101 3279 n 525 n 16800 n - 0110 6560 n 263 n 33600 n - 1000 1640 n 2101 n 8400 n - 1001 3279 n 1050 n 16800 n reset 1010 6560 n 525 n 33600 n - 1100 1640 n 4200 n 8400 n - 1101 3279 n 2101 n 16800 n - 1110 6560 n 1050 n 33600 n - shaden bits shadow register address data function initial 01 (bank 1) 3 control of versatile and clock pins 0011 xx00 select clk4 on clk4/12 output reset xx01 select clk12 on clk4/12 output - x0xx enable clk16 output pin reset x1xx set clk16 output pin to high-impedance - 0xxx set v3 output pin to high-impedance reset 1xxx enable v3 output pin - 7 control of onboard dac 0111 0000 use external dac or route audio data back into onboard dac (loopback mode) reset 0010 route audio data directly into onboard dac (non-loopback mode) - 7 ebu mute bypass control (for m1 version only) xxx0 ebu mute function not bypassed reset xxx1 ebu mute function bypassed -
2003 oct 01 49 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 01 (bank 1) a signal magnitude control for diodes d1 to d4 (lf only) 1010 0000 voltage mode: 20 mv - 0001 voltage mode: 25 mv - 0010 voltage mode: 30 mv - 0011 voltage mode: 40 mv - 0100 voltage mode: 60 mv - 0101 voltage mode: 75 mv - 0110 voltage mode: 100 mv - 0111 voltage mode: 120 mv - 1000 voltage mode: 150 mv - 1001 voltage mode: 200 mv - 1010 voltage mode: 270 mv - 1011 voltage mode: 350 mv - 1100 voltage mode: 450 mv - 1101 voltage mode: 600 mv - 1110 voltage mode: 720 mv - 1111 voltage mode: 960 mv reset 01 (bank 1) c signal magnitude control for diodes r1 and r2 (lf only) 1100 0000 voltage mode: 20 mv - 0001 voltage mode: 25 mv - 0010 voltage mode: 30 mv - 0011 voltage mode: 40 mv - 0100 voltage mode: 60 mv - 0101 voltage mode: 75 mv - 0110 voltage mode: 100 mv - 0111 voltage mode: 120 mv - 1000 voltage mode: 150 mv - 1001 voltage mode: 200 mv - 1010 voltage mode: 270 mv - 1011 voltage mode: 350 mv - 1100 voltage mode: 450 mv - 1101 voltage mode: 600 mv - 1110 voltage mode: 720 mv - 1111 voltage mode: 960 mv reset shaden bits shadow register address data function initial
2003 oct 01 50 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 table 19 bank 2 new shadow register settings (single write) shaden bits shadow register address data function initial 10 (bank 2) 3 power-down control 0011 xxx0 analog front-end active reset xxx1 analog front-end powered down - xx0x buffer ampli?er on reset xx1x buffer ampli?er off (power saving) - x0xx dac active reset x1xx dac powered down - 3 dac output mode 0xxx normal mode reset 1xxx current mode (bypass internal i-to-v converters) - 7 mechanism and voltage reference selection 0111 xx10 voltage mechanism: reset xx11 voltage mechanism: - x0xx 150 mv mechanism reset x1xx 180 mv mechanism - 7 cd-text control 0xxx ?ag all data (crc pass and fail) reset 1xxx ?ag only data that passes the crc - 1.65 v dda 3.3 v ------------------------------- - 2.5 v dda 3.3 v ---------------------------- -
2003 oct 01 51 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 10 (bank 2) a laser power control 1 1010 xxx0 approximately 58% (laser power control 2 = 0) reset approximately 72% (laser power control 2 = 1) see shadow register 3 (bank 3) xxx1 approximately 86% (laser power control 2 = 0) - approximately 100% (laser power control 2 = 1) see shadow register 3 (bank 3) a clock source xx0x bypass pll (external clock source) - xx1x select and enable pll reset a kill control x0xx disable silence injection reset x1xx enable silence injection - 0xxx internal kill reset 1xxx loop-back kill - c dc offset measurement times 1100 xx00 settling time = 354 m s reset xx01 settling tim e=1ms - xx10 settling tim e=2ms - xx11 settling time = 10 ms - c upsampler dither selection 00xx no dither selected - 01xx ac dither only - 10xx dc dither only - 11xx ac and dc dither selected reset shaden bits shadow register address data function initial
2003 oct 01 52 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 table 20 bank 3 new shadow register settings (single write) table 21 bank 3 new shadow register settings (multiple write) note 1. register elements are described in tables 26 and 27. shaden bits shadow register address data function initial 11 (bank 3) 3 diode selection for dc offset measurement 0011 x000 select d1 reset x001 select d1 - x010 select d2 - x011 select d3 - x100 select d4 - x101 select r1 - x110 select r2 - x111 select d1 - 3 laser power control 2 0xxx 60% (laser power control 1=0) reset 87% (laser power control 1=1) see shadow register a (bank 2) 1xxx 73% (laser power control 1=0) - 100% (laser power control 1=1) see shadow register a (bank 2) c enable equalizer 1100 xxx0 equalizer disabled and powered-down reset xxx1 equalizer enabled - c status pin control 000x status pin outputs decoder status register information reset 001x status pin outputs dc offset ready ?ag - 010x status pin outputs dc offset value - shaden bits shadow register address size (data nibbles) register elements (1) 11 (bank 3) 7 dc cancellation levels 0111 9 a analog fe control 1010 4
2003 oct 01 53 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 table 22 multiple write register element description shadow register element name bit numbers description 7 (bank 3) <5:0> dc offset level for d1 (reset value = 000000) <11:6> dc offset level for d2 (reset value = 000000) <17:12> dc offset level for d3 (reset value = 000000) <23:18> dc offset level for d4 (reset value = 000000) <29:24> dc offset level for r1 (reset value = 000000) <35:30> dc offset level for r2 (reset value = 000000) a (bank 3) <3:0> see table 23 <7:4> see table 24 <9:8> equaliser operating speed: 00 = 1 (reset); 01 = 2 ; 10 = 4 <15:10> see table 25 table 23 hf gain table 24 slicer threshold tracking slew rate (islice code to current conversion) data description 0000 voltage mode = 1.11 v 0001 voltage mode = 952 mv 0010 voltage mode = 588 mv 0011 voltage mode = 392 mv 0100 voltage mode = 1.11 v 0101 voltage mode = 952 mv 0110 voltage mode = 588 mv 0111 voltage mode = 392 mv 1000 voltage mode = 303 mv 1001 voltage mode = 200 mv 1010 voltage mode = 157 mv 1011 voltage mode = 107 mv 1100 voltage mode = 79 mv 1101 voltage mode = 54 mv 1110 voltage mode = 39 mv 1111 voltage mode = 27 mv data current ( m a) 0000 10 (reset) 0001 10 0010 20 0011 30 0100 50 0101 60 0110 70 0111 80 1000 100 1001 110 1010 120 1011 130 1100 150 1101 160 1110 170 1111 180
2003 oct 01 54 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 table 25 high-pass ?lter frequency cut-off level (lowest roll-off) data nominal frequency (khz) percentage deviation actual frequency (khz) 000000 10 - 37.5% 6.367 (reset) 010000 - 28.2% 7.31 001000 - 17.6% 8.395 011000 - 9.2% 9.247 000100 0% 10.186 010100 +8.6% 11.066 001100 +18% 12.023 000010 20 - 37.5% 12.706 010010 - 28.2% 14.588 001010 - 17.6% 16.520 011010 - 9.2% 18.45 000110 0% 20.324 010110 +8.6% 22.080 001110 +18% 23.988 000001 30 - 37.5% 18.967 010001 - 28.2% 21.777 001001 - 17.6% 24.660 011001 - 9.2% 27.542 000101 0% 30.339 010101 +8.6% 32.961 001101 +18% 35.318 000011 40 - 37.5% 25.003 010011 - 28.2% 29.107 001011 - 17.6% 32.961 011011 - 9.2% 36.307 000111 0% 39.994 010111 +8.6% 43.451 001111 +18% 47.206
2003 oct 01 55 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 7.17.6 s ummary of servo commands a list of the servo commands is given in table 26. these are fully compatible with the saa732x. table 26 servo commands notes 1. these commands are only available when the decoder interface is enabled. 2. and bytes are clocked out lsb first. 3. decoder status flag information in, is only valid when the internal decoder interface is enabled. commands code bytes parameters write commands write_focus_coefs1 17h 7 write_focus_coefs2 27h 7 write_focus_command 33h 3 focus_gain_up 42h 2 focus_gain_down 62h 2 write_radial coefs 57h 7 preset_latch 81h 1 radial_off c1h 1 1ch radial_init c1h 1 3ch short_jump c3h 3 long_jump c5h 5 steer_sledge b1h 1 preset_init 93h 3 write_decoder_reg (1) d1h 1 write_parameter a2h 2 read commands read_q_subcode (1)(2) 0h up to 12 read_status 70h up to 5 read_hilevel_status (3) e0h up to 4 read_aux_status f0h up to 3
2003 oct 01 56 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 7.17.7 s ummary of servo command parameters table 27 servo command parameters parameter ram address affects por value determines foc_parm_1 - focus pid - end of focus lead defect detector enabling foc_parm_2 - focus pid - focus low-pass focus error normalizing foc_parm_3 - focus pid - focus lead length minimum light level foc_int 14h focus pid - focus integrator crossover frequency foc_gain 15h focus pid 70h focus pid loop gain ca_drop 12h focus pid - sensitivity of dropout detector ramp_offset 16h focus ramp - asymmetry of focus ramp ramp_height 18h focus ramp - peak-to-peak value of ramp voltage ramp_incr - focus ramp - slope of ramp voltage fe_start 19h focus ramp - minimum value of focus error rad_parm_play 28h radial pid - end of radial lead rad_pole_noise 29h radial pid - radial low-pass rad_length_lead 1ch radial pid - length of radial lead rad_int 1eh radial pid - radial integrator crossover frequency rad_gain 2ah radial pid 70h radial loop gain rad_parm_jump 27h radial jump - ?lter during jump vel_parm1 1fh radial jump - pi controller crossover frequencies vel_parm2 32h radial jump - jump pre-de?ned pro?le speed_threshold 48h radial jump - maximum speed in fastrad mode hold_mult 49h radial jump 00h electronic damping sledge bandwidth during jump brake_dist_max 21h radial jump - maximum sledge distance allowed in fast actuator steered mode sledge_long_brake 58h radial jump ffh brake distance of sledge sledge_umax - sledge - voltage on sledge during long jump sledge_level - sledge - voltage on sledge when steered sledge_parm_1 36h sledge - sledge integrator crossover frequency sledge_parm_2 17h sledge - sledge low-pass frequencies sledge gain sledge operation mode sledge_pulse1 46h pulsed sledge - pulse width sledge_pulse2 64h pulsed sledge - pulse height defect_parm - defect detector - defect detector setting playwatchtime 54h watchdog - radial on-track watchdog time jumpwatchtime 57h watchdog - radial jump watchdog time-out
2003 oct 01 57 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 radcontrol 59h watchdog - enable/disable automatic radial off feature chip_init - set-up - enable/disable decoder interface xtra_preset 4ah set-up 38h laser on/off ra, fo and sl pdm modulating frequency fast jumping circuit on/off cd6cmd 4dh decoder interface - decoder part commands interrupt_mask 53h status pin - enabled interrupts seq_control 42h autosequencer - autosequencer control focus_start_time 5eh autosequencer - focus start time motor_start_time1 5fh autosequencer - motor start 1 time motor_start_time2 60h autosequencer - motor start 2 time radial_init_time 61h autosequencer - radial initialization time brake_time 62h autosequencer - brake time radcmdbyte 63h autosequencer - radial command byte osc_inc 68h focus/radial agc - agc control - frequency of injected signal phase_shift 67h focus/radial agc - phase shift of injected signal level1 69h focus/radial agc - amplitude of signal injected level2 6ah focus/radial agc - amplitude of signal injected agc_gain 6ch focus/radial agc - focus/radial gain parameter ram address affects por value determines
2003 oct 01 58 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 8 summary of servo command parameters values table 28 foc_parm1 parameter: focus end lead frequency, defect detector, offtrack detector table 29 foc_parm2 parameter: focus low-pass start frequency, focusing system foc_parm1 focus end lead frequency f 3 khz foc_pole_lead value (binary) xxx1 1100 1.97 xxx1 1000 2.29 xxx0 0000 2.61 xxx0 1000 2.94 xxx0 1100 3.26 xxx1 1101 3.90 xxx1 1001 4.55 xxx0 0001 5.19 xxx0 1001 5.82 xxx0 1101 6.46 xxx1 1110 7.72 xxx1 1010 8.98 xxx0 0010 10.22 xxx0 1010 11.46 xxx0 1110 12.69 xxx1 1111 15.13 xxx1 1011 17.54 xxx0 0011 19.93 xxx0 1011 22.28 defect_det_sw defect detector x11x xxxx defect detector does not in?uence focus and radial x10x xxxx focus hold on defect detector x00x xxxx focus and radial hold on defect detector x01x xxxx unde?ned, reserved otd_select offtrack detector 0xxx xxxx on track active 1 1xxx xxxx on track active 0 foc_parm2 focus low-pass start frequency f 4 khz foc_pole_noise value (binary) xxx1 1100 3.90 xxx1 1000 4.55 xxx0 0000 5.19 xxx0 1000 5.82 xxx0 1100 6.46 xxx1 1101 7.72 xxx1 1001 8.98 xxx0 0001 10.22 xxx0 1001 11.46 xxx0 1101 12.69 xxx1 1110 15.13 xxx1 1010 17.54 xxx0 0010 19.93 xxx0 1010 22.28 xxx0 1110 25.40 xxx1 1111 30.26 xxx1 1011 35.08 xxx0 0011 39.86 xxx0 1011 44.56 detector_arr focusing system xx1x xxxx single foucault xx0x xxxx double foucault
2003 oct 01 59 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 table 30 foc_parm3 parameter: focus lead length, ca start level for focus acquisition table 31 ca_drop parameter: ca level for dropout detection table 32 fe_start parameter: minimum threshold for focus start table 33 foc_int_strength parameter: focus integrator strength table 34 foc_gain parameter: focus gain foc_parm3 focus lead length f 3 /f 2 foc_lead_length value (binary) 0000 xxx1 64 1000 xxx1 32 0100 xxx1 21.3 1100 xxx1 16 0010 xxx1 12.8 1010 xxx1 10.7 0110 xxx1 9.1 1110 xxx1 8 0001 xxx1 7.1 1001 xxx1 6.4 0101 xxx1 5.8 1101 xxx1 5.3 0011 xxx1 4.9 1011 xxx1 4.6 0111 xxx1 4.3 1111 xxx1 4 ca_start value (binary) ca min xxxx 000x 0.0225 xxxx 001x 0.03 xxxx 010x 0.045 xxxx 011x 0.06 xxxx 100x 0.09 xxxx 101x 0.125 xxxx 110x 0.18 xxxx 111x 1.0 ca_drop value (binary) ca min xxx0 0000 0.0225 xxx0 0100 0.03 xxx0 1000 0.045 xxx0 1100 0.06 xxx1 0000 0.09 xxx1 0100 0.125 xxx1 1000 0.18 xxx1 1100 1.0 fe_start value (decimal) minimum threshold for (d 1 - d 2 )/(d 1 +d 2 ) 0 always 1 1/127 2 2/127 i i/127 64 64/127 65...127 65 to 127/127 127 continuous ramping 128...255 not allowed foc_int_strength value (decimal) focus integrator strength f 5 hz 0 integrator hold 1 1.2 2 2.4 i 1.2 i 21 25 22...255 unde?ned foc_gain value (decimal) g 1 2048 2 1024 3 2048/3 i 2048/i 255 2048/255 0 unde?ned
2003 oct 01 60 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 table 35 rad_pole_noise parameter: radial low-pass start frequency table 36 rad_lead_length parameter: radial lead length rad_pole_noise value (binary) radial low-pass start frequency f 4 khz 1101 1100 3.90 1011 1000 4.55 1010 0000 5.19 1010 1000 5.82 1000 1100 6.46 1001 1101 7.72 1001 1001 8.98 0100 0001 10.22 0100 1001 11.46 0100 1101 12.69 0101 1110 15.13 0101 1010 17.54 0100 0010 19.93 0100 1010 22.28 xxx0 1110 25.40 xxx1 1111 30.26 xxx1 1011 35.08 xxx0 0011 39.86 xxx0 1011 44.56 rad_lead_length value (binary) rad_lead_length value (hex) radial lead length f 3 /f 2 0000 xxxx 0x 128 1000 xxxx 8x 64 0100 xxxx 4x 42.7 1100 xxxx cx 32 0010 xxxx 2x 25.6 1010 xxxx ax 21.3 0110 xxxx 6x 18.3 1110 xxxx ex 16 0001 xxxx 1x 14.2 1001 xxxx 9x 12.8 0101 xxxx 5x 11.6 1101 xxxx dx 10.7 0011 xxxx 3x 9.8 1011 xxxx bx 9.1 0111 xxxx 7x 8.5 1111 xxxx fx 8
2003 oct 01 61 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 table 37 rad_parm_play, rad_parm_jump parameters: radial end lead frequency table 38 rad_gain parameter: radial pid gain table 39 rad_int_strength parameter: radial integrator strength table 40 sledge_parm1 parameter: sledge integrator bandwidth, shock ?lter (low-pass, high-pass selection); ram address 36h rad_parm_play rad_parm_jump value (binary) rad_parm_play rad_parm_jump value (hex) radial end lead frequency f 3 khz 1101 1100 dc 1.97 1101 1000 d8 2.29 1100 0000 c0 2.61 1100 1000 c8 2.94 1100 1100 cc 3.26 1101 1101 dd 3.90 1001 1001 99 4.55 1010 0001 a1 5.19 1010 1001 a9 5.82 1010 1101 ad 6.46 1001 1110 9e 7.72 0101 1010 5a 8.98 0100 0010 42 10.22 0100 1010 4a 11.46 1000 1110 8e 12.69 0101 1111 5f 15.13 0101 1011 5b 17.54 0100 0011 43 19.93 0100 1011 4b 22.28 rad_gain value (decimal) radial pid gain g 1 256 2 256/2 3 256/3 i 256/i 255 256/255 0 unde?ned rad_int_strength value (decimal) radial integrator strength f 5 hz 0 integrator hold 1 0.3 2 0.6 i 0.31 i 255 79.05 sledge_parm1 sledge integrator f 1 hz sledge_int x00x xxxx integrator disabled x10x xxxx 0.15 x01x xxxx 0.31 x11x xxxx 0.45
2003 oct 01 62 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 table 41 sledge_parm2 parameter: sledge gain, low-pass frequencies, operation mode; ram address 17h table 42 sledge_pulse1 parameter: sledge pulse high time, low time; ram address 46h sledge_parm2 sledge gain g s sledge_gain 0xxx x000 0.218 0xxx x001 0.281 0xxx x010 0.436 0xxx x011 0.562 0xxx x100 0.875 0xxx x101 1.125 0xxx x110 1.750 0xxx x111 2.250 1xxx x000 3.500 1xxx x001 4.500 1xxx x010 7.000 1xxx x011 9.000 1xxx x100 14.00 1xxx x101 18.00 1xxx x110 28.00 1xxx x111 36.00 sledge_low_pass sledge low-pass frequency f 2 hz x00x 0xxx 5.0 x10x 0xxx 10.1 x01x 0xxx 15.3 x11x 0xxx 20.5 x00x 1xxx 0.3 x10x 1xxx 0.6 x01x 1xxx 0.9 x11x 1xxx 1.2 sledge_op_mode sledge operation mode xxx0 0xxx pi mode operation xxx0 1xxx pulsed mode operation, microcontroller controlled xxx1 1xxx pulsed mode operation, automatic mode sledge_pulse1 hex time low ms time_lo 0000 xxxx 0x 0 0001 xxxx 1x 2 0010 xxxx 2x 4 0011 xxxx 3x 6 0100 xxxx 4x 8 0101 xxxx 5x 10 0110 xxxx 6x 12 0111 xxxx 7x 14 1000 xxxx 8x 16 1001 xxxx 9x 18 1010 xxxx ax 20 1011 xxxx bx 22 1100 xxxx cx 24 1101 xxxx dx 26 1110 xxxx ex 28 1111 xxxx fx 30 time_hi time high ms xxxx 0000 x0 0 xxxx 0001 x1 2 xxxx 0010 x2 4 xxxx 0011 x3 6 xxxx 0100 x4 8 xxxx 0101 x5 10 xxxx 0110 x6 12 xxxx 0111 x7 14 xxxx 1000 x8 16 xxxx 1001 x9 18 xxxx 1010 xa 20 xxxx 1011 xb 22 xxxx 1100 xc 24 xxxx 1101 xd 26 xxxx 1110 xe 28 xxxx 1111 xf 30
2003 oct 01 63 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 table 43 sledge_pulse2 parameter: sledge pulse height; ram address 64h table 44 vel_parm1 parameter: gain constant for short jump, integrator cross-over frequency during jump; ram address 1fh table 45 vel_parm2 parameter: time constant during sledge access/actuator access, minimum jump speed during short jump; ram address 32h sledge_pulse2 hex pulse height 0111 1111 78 full-scale, positive .... .... 0100 0000 40 half-scale, positive a level = a/7f, positive 0000 0000 00 zero .... .... 1000 0000 80 full-scale, negative vel_parm1 hex gain constant for short jump k v vel_prop 0000 xxxx 0x 0.1875 1000 xxxx 8x 0.4375 0100 xxxx 4x 0.6875 1100 xxxx cx 0.9375 0010 xxxx 2x 1.1875 1010 xxxx ax 1.4375 0110 xxxx 6x 1.6875 1110 xxxx ex 1.9375 0001 xxxx 1x 2.1875 1001 xxxx 9x 2.4375 0101 xxxx 5x 2.6875 1101 xxxx dx 2.9375 0011 xxxx 3x 3.1875 1011 xxxx bx 3.4375 0111 xxxx 7x 3.6875 1111 xxxx fx 3.9375 vel_int integrator cross-over frequency during jump f 0 xxxx 0000 x0 integrator hold xxxx 0001 x1 10.0/k v xxxx 0010 x2 20.0/k v xxxx 0011 x3 30.0/k v ii 10.0/k v xxxx 1111 xf 150.0/k v vel_parm2 hex deceleration time fast actuator steered ms deceleration time sledge steered ms vel_setp (binary) 0000 xxxx 0x 7.5 7.5 1000 xxxx 8x 8.2 8.2 0100 xxxx 4x 9 9 1100 xxxx cx 9.7 9.7 0010 xxxx 2x 10.5 10.5 1010 xxxx ax 11.2 11.2 0110 xxxx 6x 12.5 12.5 1110 xxxx ex 14 14 0001 xxxx 1x 15.5 15.5 1001 xxxx 9x 16.5 16.5 0101 xxxx 5x 20.7 20.7 1101 xxxx dx 25 25 0011 xxxx 3x 31.2 31.2 1011 xxxx bx 41 41 0111 xxxx 7x 63 63 1111 xxxx fx 128 128 vel_min v 1 minimum jump speed khz xxxx 0000 x0 0.0 xxxx 0001 x1 1.0 xxxx 0010 x2 2.0 xxxx 0011 x3 3.0 xxxx 0100 x4 4.0 xxxx 0101 x5 5.0 xxxx 0110 x6 6.0 xxxx 0111 x7 7.0 xxxx 1xxx unde?ned vel_parm1 hex gain constant for short jump k v vel_prop
2003 oct 01 64 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 table 46 brake_dist_max parameter: maximum sledge distance allowed in fast actuator steered mode; ram address 21h table 47 sledge_umax parameter: voltage on sledge during long jump table 48 sledge_level parameter: voltage on sledge when steered table 49 jumpwatchtime parameter: radial jump watchdog readout time difference; ram address 57h table 50 playwatchtime parameter: radial play watchdog maximum time-out; ram address 54h table 51 radcontrol parameter: automatic radial servo switch-off control; ram address 59h brake_dist_max value (decimal) maximum sledge distance allowed in fast actuator steered mode, number of tracks 0...127 not allowed - 11 16 - 22 16 .... .... - ii 16 .... .... - 127 127 16 - 128 128 16 sledge_umax (decimal) voltage on sledge 127 255/256 v dd i (i + 128)/256 v dd 0 0.5 v dd - 1 (128 - 1)/256 v dd - i( - i + 128)/256 v dd - 128 0 sledge_level (decimal) voltage on sledge 127 127/256 v dd i i/256 v dd 00 - 1 - 1/256 v dd - i - i/256 v dd - 128 - 128/256 v dd jumpwatchtime radial jump watchdog readout time difference ms 80h to ffh none 0h 0 1h 0.25 ii 0.25 7fh 32 playwatchtime radial play watchdog maximum time-out ms 80h 0 81h 0.5 82h 1 i(i - 80h) 0.5 00h 64 j (j + 80h) 0.5 7fh 128 radcontrol hex automatic radial servo switch-off control 0000 0000 00 radial servo not in?uenced by watchdog 0100 0000 40 switch-off radial servo on jump error; no action on play error 0010 0000 20 switch-off radial servo on play error; no action on jump error 0110 0000 60 switch-off radial servo on play or jump error
2003 oct 01 65 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 table 52 hold_mult parameter: velocity proportional part during long jump, sledge gain in steered sledge mode; ram address 49h table 53 speed_threshold parameter: maximum sledge speed allowed in fast actuator steered mode; ram address 48h table 54 sledge_long_brake parameter: maximum sledge distance allowed in sledge steered mode; ram address 58h hold_mult hex velocity proportional part during long jump k p vel_prop1 (binary) 0000 xxxx 0x 0 1000 xxxx 8x 0.015625 0100 xxxx 4x 0.031250 1100 xxxx cx 0.046875 0010 xxxx 2x 0.062500 1010 xxxx ax 0.078125 0110 xxxx 6x 0.093750 1110 xxxx ex 0.109375 0001 xxxx 1x 0.125000 1001 xxxx 9x 0.140625 0101 xxxx 5x 0.156250 1101 xxxx dx 0.171875 0011 xxxx 3x 0.187500 1011 xxxx bx 0.203125 0111 xxxx 7x 0.218750 1111 xxxx fx 0.234375 vel_prop2 sledge gain in steered mode g s xxxx x000 x0 2 xxxx x001 x1 3 xxxx x010 x2 4 xxxx x011 x3 6 xxxx x100 x4 8 xxxx x101 x5 12 xxxx x110 x6 16 xxxx x111 x7 24 speed_threshold value (decimal) maximum sledge speed allowed in fast actuator steered mode, number of tracks (x 1000 tracks/sec) 0...127 not allowed - 11 - 22 - 3... - 127 3...127 - 128 128 - 64 reset value sledge_long_brake (decimal) maximum sledge distance allowed in sledge steered mode, number of tracks - 1... - 128 test always true 11 128 22 128 3...62 3 128...62 128 63 63 128 - 1 reset value
2003 oct 01 66 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 table 55 defect_parm parameter: defect detector control table 56 interrupt_mask parameter: mask to enable interrupt in interrupt status register; ram address 53h table 57 time_parameter: timer interrupt values note 1. the time_parameter values are also used for focus_start_time, motor_start_time1, motor_start_time2, radial_init_time and brake_time. table 58 phase_shift parameter: focus/radial agc detection phase shift; ram address 67h note 1. the value a is the value programmed in table 60 as the 6 lsbs of osc_inc. defect_parm fast ?lter bandwidth xxxx xx00 3500 hz xxxx xx01 7000 hz xxxx xx10 14000 hz xxxx xx11 reserved for future use defect_parm slow ?lter time constant alpha value xxxx 10xx 16 ms 0.00006 xxxx 11xx 8 ms 0.00012 xxxx 00xx 4 ms 0.00024 xxxx 01xx 2 ms 0.00048 defect_parm coef?cient b value xx00 xxxx 0.25 xx01 xxxx 0.125 xx10 xxxx 0.0625 xx11 xxxx reserved for future use defect_parm defect detector maximum on time 00xx xxxx 1.0 ms 01xx xxxx 1.5 ms 10xx xxxx 2.0 ms 11xx xxxx 2.5 ms interrupt_mask interrupt enabled 0000 0000 no interrupt xxxx xxx1 focus lost xxxx xx1x subcode ready xxxx x1xx subcode absolute seconds changed xxxx 1xxx subcode discontinuity xxx1 xxxx radial error xx1x xxxx autosequencer state changes x1xx xxxx autosequencer error time_parameter value (decimal) (1) timer interrupt values wait time (ms) 129 i 143 4.26 (i - 128) 144 i 159 68.2 + 4.57 (i - 144) 160 i 175 141.4 + 4.92 (i - 160) 176 i 191 224.1 + 5.33 (i - 176 192 i 207 305.4 + 5.82 (i - 192 208 i 223 398.5 + 6.40 (i - 208) 224 i 239 500.8 + 7.11 (i - 224 2402 i 55 614.6 + 8.00 (i - 240) 0 i 15 742.6 + 9.11 i 16 i 31 888.9 + 10.6 (i - 16) 32 i 47 1059 + 12.8 (i - 32) 48 i 63 1263 + 16.0 (i - 48) 64 i 79 1519 + 21.2 (i - 64) 80 i 95 1860 + 32.0 (i - 80) 96 i 111 2372 + 64.0 (i - 96) 111 3398.0 112...127 in?nite phase_shift (decimal) focus/radial agc detection phase shift ( m s) (deg) 00 0 1 a (1) 60.47 180 (a/128) 2 a 120.94 180 (2 a/128) i ai 60.47 180 (i a/128) 128 180 - 1 a - 60.47 - 180 (a/128) - 2 a - 120.94 - 180 (2 a/128) - i a - i 60.47 - 180 (i a/128) 128 180
2003 oct 01 67 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 table 59 level1, level2 parameter: amplitude of signal injected into focus/radial agc; ram address level1 = 69h, level2 = 6ah table 60 osc_inc parameter: focus/radial agc system control, oscillator frequency; ram address 68h table 61 re_offset parameter: initial value setting table 62 re_gain parameter: initial value setting table 63 sum_gain parameter: initial value setting level1, level2 (decimal) amplitude of injected signal 00 1 to 126 higher 127 highest 128 to 255 not allowed osc_inc oscillator frequency hz xx00 0000 0 xx00 0001 64.6 xx00 0010 129.2 xx00 0011 193.8 aa 64.6 xx11 1111 4069.8 agc control 00xx xxxx agc system off 11xx xxxx focus agc active 01xx xxxx radial agc active re_offset value 127 128/256 i i/256 00 - i - i/256 - 128 - 128/256 re_gain value - 128 not allowed - 127 1/256 - i( - i + 128)/256 - 1 127/256 0 128/256 1 129/256 i (i + 128)/256 127 255/256 sum_gain value - 128 not allowed - 127 1/256 - i( - i + 128)/256 - 1 127/256 0 128/256 1 129/256 i (i + 128)/256 127 255/256
2003 oct 01 68 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 9 limiting values in accordance with the absolute maximum rating system (iec 60134). notes 1. must not exceed 4.2 v. 2. including voltage on outputs in 3-state mode. 3. only valid when both supply voltages are present. 4. the peak current is limited to 25 times the corresponding maximum current. 5. human body model. 6. machine model. symbol parameter conditions min. max. unit v ddd digital supply voltage internal rail - 0.5 +2.5 v external rail - 0.5 +4.6 v v i(max) maximum input voltage any input notes 1, 2 and 3 - 0.5 v ddd + 0.5 v 5 v tolerant pins - 0.5 +6.0 v v o any output voltage - 0.5 v ddd v i ddd digital supply current per supply pin note 4 - 20 ma i ssd digital ground current per supply pin note 4 - 20 ma v es electrostatic handling voltage note 5 - 2000 +2000 v note 6 - 200 +200 v t amb ambient temperature 0 70 c t stg storage temperature - 55 +125 c
2003 oct 01 69 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 10 characteristics v ddd = 1.65 to 1.95 v; v dda = 3.0 to 3.6 v; v ss =0v; t amb = 0 to 70 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supplies v ddd digital supply voltage 1.65 1.8 1.95 v i ddd digital supply current n = 1 mode - 4.0 - ma n = 2 mode - 5.0 - ma n = 4 mode - 6.0 - ma v dda analog supply voltage 3.0 3.3 3.6 v i dda analog supply current n = 1 mode - 34 - ma n = 2 mode - 34 - ma n = 4 mode - 34 - ma dem dac output (v pos = 3.3 v, v ss =0v, v neg = 0 v and t amb =25 c) d ifferential outputs : pins dacln, daclp, dacrn and dacrp s/n signal-to-noise ratio note 1 - 90 - db (thd + n)/s total harmonic distortion plus noise-to-signal ratio note 2 --- 80 db headphone buffer (v pos = 3.3 v, v ss =0v, v neg = 0 v and t amb =25 c) o utputs : pins bufoutr and bufoutl s/n signal-to-noise ratio - 85 - db (thd + n)/s total harmonic distortion plus noise-to-signal ratio note 3 --- 80 db i nputs : pins bufinr and bufinl z i input impedance - 47 - k w servo and decoder analog functions (v dda = 3.3 v, v ssa = 0 v and t amb =25 c) r eference generator : pin i ref v iref reference voltage level 1.16 1.26 1.36 v i ref input reference current - 50 -m a r iref(ext) external resistance - 24 - k w d iode voltage input : pins d1 to d4, r1 and r2 v i(d)(max) maximum input voltage for central diode input signal voltage mode 0 - 960 mv v i(r)(max) maximum input voltage for satellite diode input signal voltage mode 0 - 960 mv v ref(int) internally generated reference voltage v ref_sel =10 - note 4 - v v ref_sel =11 - note 5 - v b hf high frequency bandwidth (d1 to d4) at 0 db 5 -- mhz g tol(hf) high frequency gain tolerance - 20 - +20 %
2003 oct 01 70 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 b lf low frequency bandwidth (d1 to d4, r1 and r2) at 0 db 20 -- khz (thd + n)/s lf low frequency total harmonic distortion plus noise-to-signal ratio at 0 db -- 50 - 40 db s/n lf low frequency signal-to-noise ratio 55 -- db g tol(lf) low frequency gain tolerance - 20 - +20 % d g v(lf) low frequency variation of gain between channels - 3 - +3 % a cs(lf) low frequency channel separation - 60 - db laser drive circuit (v dda = 3.3 v; v ssa =0v; t amb =25 c; r iref =30k w ) i o(laser) output current v laser =1v - (v dda - 0.6 v) 10 50 120 ma snr signal-to-noise ratio i o = 50 ma; b = 20 mhz - 40 - db i lfpower(max) maximum laser supply current i o = 120 ma -- 140 ma v monitor1 monitor diode voltage 1 maximum power; sel180 = 0 140 150 160 mv v monitor2 monitor diode voltage 2 maximum power; sel180 = 1 170 180 190 mv r i input resistance 10 -- m w v sense sense voltage - 100 - +100 mv p step laser output power range 43 - 100 % i pd power-down supply current -- 10 m a i laser(off) laser off current -- 30 m a digital inputs p in reset (5 v tolerant ; ttl inputs with pull - up resistor and hysteresis ) v ih high-level input voltage 2.0 -- v v il low-level input voltage -- 0.8 v v hys hysteresis voltage 0.3 -- v i pu pull-up current v i = 0 to v ddd ; notes 6 and 7 - 31 -- 68 m a t w(l) pulse width (active low) reset only 1 --m s p ins v1 and v2 (cmos inputs ) v ih high-level input voltage 2.0 -- v v il low-level input voltage -- 0.8 v symbol parameter conditions min. typ. max. unit
2003 oct 01 71 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 p ins test1 to test4 (5 v tolerant ; ttl inputs with pull - down resistors ) v ih high-level input voltage 2.0 -- v v il low-level input voltage -- 0.8 v i pd pull-down current v i = 0 to v ddd ; notes 6 and 7 (v i =5v; note 8) 20 50 75 m a p ins rck, wcli, sdi and scli (5 v tolerant ; ttl inputs ) v ih high-level input voltage 2.0 -- v v il low-level input voltage -- 0.8 v i il low-level input current v i = 0; no pull-up -- 1 m a i ih high-level input current v i =v ddd ; no pull-down -- 1 m a pins scl, sild, rab and cdtclk (5 v tolerant ttl inputs with hysteresis ) v ih high-level input voltage 2.0 -- v v il low-level input voltage -- 0.8 v i il low-level input current v i = 0; no pull-up -- 1 m a i ih high-level input current v i =v dde ; no pull-down -- 1 m a v hys hysteresis voltage 0.3 -- v 3-state outputs pins sclk, wclk, data, clk16, ra, fo, sl, sbsy, sfsy, clk4/12, status, moto1 and moto2 (5 v tolerant cmos outputs ;10ns slew rate limited ) v ol low-level output voltage i ol =4ma -- 0.4 v v oh high-level output voltage i oh = - 4ma v ddd - 0.4 -- v i ol low-level output current v ol = 0.4 v; note 9 4 -- ma i oh high-level output current v ol =v ddd - 0.4 v; note 9 - 4 -- ma t tran(l-h) low-to-high transition time c l = 30 pf 10.2 - 14.5 ns i oz 3-state leakage current v i = 0; no pull-up or pull-down -- 1 m a pins dobm, v4 and v5 (5 v tolerant cmos outputs ;5ns slew rate limited ) v ol low-level output voltage i ol =4ma -- 0.4 v v oh high-level output voltage i oh = - 4ma v ddd - 0.4 -- v i ol low-level output current v ol = 0.4 v; note 9 4 -- ma i oh high-level output current v ol =v ddd - 0.4 v; note 9 - 4 -- ma t tran(l-h) low-to-high transition time c l =30pf - 10 13.8 ns i oz 3-state leakage current v i = 0; no pull-up or pull-down -- 1 m a symbol parameter conditions min. typ. max. unit
2003 oct 01 72 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 digital inputs and outputs pin v3 (5 v tolerant ; ttl input ;3- state output ) v ih high-level input voltage 2.0 -- v v il low-level input voltage -- 0.8 v i il low-level input current v i = 0; no pull-up -- 1 m a i ih high-level input current v i =v ddd ; no pull-down -- 1 m a v ol low-level output voltage i ol =4ma -- 0.4 v v oh high-level output voltage i oh = - 4ma v ddd - 0.4 -- v i ol low-level output current v ol = 0.4 v; note 9 4 -- ma i oh high-level output current v ol =v ddd - 0.4 v; note 9 - 4 -- ma t tran(l-h) low-to-high transition time c l = 30 pf 2.6 - 6.3 ns i oz 3-state leakage current v i =0 -- 1 m a pins lkill, rkill and cflag (5 v tolerant ; ttl input with pull - up ;3- state open - drain output ;10ns slew rate limited ) v ih high-level input voltage 2.0 -- v v il low-level input voltage -- 0.8 v i pu pull-up current v i = 0 to v ddd ; notes 6 and 7 - 13 -- 36 m a v ol low-level output voltage i ol =4ma -- 0.4 v v oh high-level output voltage i oh = - 4ma v ddd - 0.4 -- v i ol low-level output current v ol = 0.4 v; note 9 4 -- ma i oh high-level output current v ol =v ddd - 0.4 v; note 9 - 4 -- ma t tran(l-h) low-to-high transition time c l = 30 pf 8.6 10 13.8 ns i oz 3-state leakage current v i =0 -- 1 m a pins cdtrdy, cdtdata, ef and sub (5 v tolerant ; ttl input ;3- state output ;10ns slew rate limited ) v ih high-level input voltage 2.0 -- v v il low-level input voltage -- 0.8 v i il low-level input current v i =0 -- 1 m a i ih high-level input current v i =v ddd -- 1 m a v ol low-level output voltage i ol =4ma -- 0.4 v v oh high-level output voltage i oh = - 4ma v ddd - 0.4 -- v i ol low-level output current v ol = 0.4 v; note 9 4 -- ma i oh high-level output current v ol =v ddd - 0.4 v; note 9 - 4 -- ma t tran(l-h) low-to-high transition time c l = 30 pf 8.6 10 13.8 ns i oz 3-state leakage current v i =0 -- 1 m a symbol parameter conditions min. typ. max. unit
2003 oct 01 73 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 notes 1. assumes use of external components as shown in the application diagram; see fig.38. 2. r l =10k w . 3. r l =1k w . 4. the typical value is as follows: 5. the typical value is as follows: 6. pull-up/down devices are protected by a pass-gate and do not behave as a normal resistor for external applications 7. pull-up/down resistors are connected to external power supply (v dde /gnd). 8. minimum condition for v i = 4.5 v, maximum condition for v i = 5.5 v. 9. accounts for 100 mv voltage drop in both supply lines. 10. minimum condition for v tol = 4.5 v, maximum condition for v tol = 5.5 v. 11. leakage path from pad to ground. pin sda (5 v tolerant ; 400 kh z i 2 c- bus pad ) v ih high-level input voltage 0.7v tol -- v v il low-level input voltage v tol = 5 v; note 10 -- 0.3v tol v v hys hysteresis voltage 0.05v tol -- v v ol low-level output voltage i ol =3ma -- 0.4 v t f output fall time from v ih to v il bus capacitance, c b , from 10 pf to 400 pf) 20 + 0.1c b - 250 ns i ikg steady-state current input signal v i =v ddd ; note 11 - 24 m a v i = 5 v; note 11 - 10 22 m a crystal oscillator i nput : pin oscin ( external clock ) v ih high-level input voltage -- 0.2v ddd v v il low-level input voltage 0.8v ddd -- v o utput : pin oscout; see fig.4 v ol low-level output voltage -- 0.4 v v oh high-level output voltage 0.85v ddd -- v f xtal crystal frequency 100 ppm - 8.4672 - mhz g m mutual conductance at start-up 19.1 - 23.0 ma/v symbol parameter conditions min. typ. max. unit 1.65 3.3 v dda ------------------------- - 2.5 3.3 v dda ----------------------
2003 oct 01 74 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 11 operating characteristics (subcode interface timing) v ddd = 1.65 to 1.95 v; v ss =0v; t amb = 0 to 70 c; unless otherwise speci?ed. note 1. in the normal operating mode the subcode timing is directly related to the overspeed factor n. in the lock-to-disc mode n is replaced by the disc speed factor d, symbol parameter conditions min. typ. max. unit subcode interface timing (single speed n); see fig.34; note 1 i nput : pin rck t clkh input clock high time 2/n 4/n 6/n m s t clkl input clock low time 2/n 4/n 6/n m s t r input clock rise time -- 80/n ns t f input clock fall time -- 80/n ns t d(sfsy-rck) delay time sfsy to rck 10/n - 20/n m s o utputs : pins sbsy, sfsy and sub (c l = 20 pf) t cy(block) block cycle time 12.0/n 13.3/n 14.7/n ms t w(sbsy) sbsy pulse width -- 300/n m s t cy(frame) frame cycle time 122/n 136/n 150/n m s t w(sfsy) sfsy pulse width 3-wire mode -- 366/n m s t sfsyh sfsy high time -- 66/n m s t sfsyl sfsy low time -- 84/n m s t d(sfsy-sub) delay time sfsy to sub (p data) valid -- 1/n m s t d(rck-sub) delay time rck falling to sub -- 0 m s t h(rck-sub) hold time rck to sub -- 0.7/n m s
2003 oct 01 75 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 handbook, full pagewidth t w(sbsy) t w(sfsy) t r v dd ?0.8 v v dd ?0.8 v t sfsyl t sfsyh t cy(block) t cy(frame) t f t d(sfsy - rck) t d(sfsy - sub) t h(rck - sub) t d(rck - sub) sbsy sfsy rck sub sfsy (4-wire mode) sfsy (3-wire mode) 0.8 v 0.8 v 0.8 v mgl718 fig.34 subcode interface timing diagram.
2003 oct 01 76 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 12 operating characteristics (i 2 s-bus timing) v ddd = 1.65 to 1.95 v; v ss =0v; t amb = 0 to 70 c; unless otherwise speci?ed. note 1. in the normal operating mode the i 2 s-bus timing is directly related to the overspeed factor n. in the lock-to-disc mode n is replaced by the disc speed factor d. symbol parameter conditions min. typ. max. unit i 2 s-bus timing (single speed n); see fig.35; note 1 c lock output : pin sclk (c l = 20 pf) t cy output clock period sample rate = f s - 472.4/n - ns sample rate = 2f s - 236.2/n - ns sample rate = 4f s - 118.1/n - ns t ch clock high time sample rate = f s 166/n -- ns sample rate = 2f s 83/n -- ns sample rate = 4f s 42/n -- ns t cl clock low time sample rate = f s 166/n -- ns sample rate = 2f s 83/n -- ns sample rate = 4f s 42/n -- ns o utputs : pins wclk, data and ef (c l =20pf) t su set-up time sample rate = f s 95/n -- ns sample rate = 2f s 48/n -- ns sample rate = 4f s 24/n -- ns t h hold time sample rate = f s 95/n -- ns sample rate = 2f s 48/n -- ns sample rate = 4f s 24/n -- ns dd v ?0.8 v 0.8 v dd v ?0.8 v 0.8 v t ch mbg407 t cl clock period t cy sclk wclk data ef t h t su fig.35 i 2 s-bus timing diagram.
2003 oct 01 77 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 13 operating characteristics (microcontroller interface timing) v dd = 1.65 to 1.95 v; v ss =0v; t amb = 0 to 70 c; unless otherwise speci?ed. symbol parameter conditions normal mode lock-to-disc mode unit min. max. min. max. microcontroller interface timing (4-wire bus mode; writing to decoder registers 0 to f; reading q-channel subcode and decoder status); see figs.36 and 37; note 1 i nputs scl and rab t cl input clock low time 480/n + 20 - 2400/n + 20 - ns t ch input clock high time 480/n + 20 - 2400/n + 20 - ns t r input rise time - 480/n - 480/n ns t f input fall time - 480/n - 480/n ns r ead mode (c l = 20 pf) t drd delay time rab to sda valid - 50 - 50 ns t pd propagation delay scl to sda 720/n - 20 960/n + 20 720/n + 20 4800/n + 20 t drz delay time rab to sda high-impedance - 50 - 50 ns w rite mode (c l = 20 pf) t sud set-up time sda to scl note 2 20 - 720/n - 20 - 720/n - ns t hd hold time scl to sda - 960/n + 20 - 4800/n + 20 ns t sucr set-up time scl to rab 240/n + 20 - 1200/n + 20 - ns t dwz delay time sda to rab high-impedance 0 - 0 - ns microcontroller interface timing (4-wire bus mode; servo commands); see figs.36 and 38; note 2 i nputs scl and sild t l input low time 710 - 710 - ns t h input high time 710 - 710 - ns t r input rise time - 240 - 240 ns t f input fall time - 240 - 240 ns r ead mode (c l = 20 pf) t dld delay time sild to sda valid - 25 - 25 ns t pd propagation delay scl to sda - 950 - 950 ns t dlz delay time sild to sda high-impedance - 50 - 50 ns t suclr set-up time scl to sild 480 - 480 - ns
2003 oct 01 78 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 notes 1. the 4-wire bus mode microcontroller interface timing for writing to decoder registers 0 to f, and reading q-channel subcode and decoder status, is a function of the overspeed factor n. in the lock-to-disc mode the maximum data rate is lower. 2. negative set-up time means that the data may change after clock transition. t hclr hold time sild to scl 830 - 830 - ns w rite mode (c l = 20 pf) t sd set-up time sda to scl 0 - 0 - ns t hd hold time scl to sda 950 - 950 - ns t scl set-up time scl to sild 480 - 480 - ns t hcl hold time sild to scl 120 - 120 - ns t dplp delay between two sild pulses 70 - 70 - ns t dwz delay time sda to sild high-impedance 0 - 0 - ns symbol parameter conditions normal mode lock-to-disc mode unit min. max. min. max. sda (saa782x) scl rab t r dd v ?0.8 v 0.8 v t r t f t f dd v ?0.8 v 0.8 v dd v ?0.8 v 0.8 v t pd t cl t ch t drd t drz high-impedance mbl451 fig.36 4-wire microcontroller timing; read mode (q-channel subcode and decoder status information).
2003 oct 01 79 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 handbook, full pagewidth scl rab t r t f dd v ?0.8 v 0.8 v dd v ?0.8 v 0.8 v t hd t cl t ch t dwz mbg405 t r t f dd v ?0.8 v 0.8 v t cl t ch t sucr t sud sda (microcontroller) high-impedance fig.37 4-wire bus microcontroller timing; write mode (decoder registers 0 to f).
2003 oct 01 80 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 handbook, full pagewidth t dld t hclr t suclr t pd t dlz 0.8 v 0.8 v 0.8 v v dd C 0.8 v v dd C 0.8 v v dd C 0.8 v sild scl sda (saa782x) mbl452 fig.38 4-wire bus microcontroller timing; read mode (servo commands).
2003 oct 01 81 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 handbook, full pagewidth t dplp t l t scl t dwz t hcl t h t hd t sd t l 0.8 v 0.8 v 0.8 v v dd - 0.8 v v dd ?0.8 v v dd ?0.8 v sild scl sda (microcontroller) mbg416 fig.39 4-wire bus microcontroller timing; write mode (servo commands).
2003 oct 01 82 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 14 application information handbook, full pagewidth SAA7824hl mbl453 laser test4 test3 test2 test1 v5 v4 v3 dacgnd 21 22 23 24 25 26 27 28 79 78 77 76 75 74 73 80 dacrp dacrn dacv ref dacln daclp dacv pos bufv pos lfpower exfilter monitor sense v ssa1 i ref v dda1 v refo d1 d2 d3 d4 r1 r2 cslice v dda2 v ssa2 oscout 8.4672 mhz 24 k w (0.5 w) r8 v ssd v ssd oscin v ssa3 3 1 2 6 4 5 9 7 8 12 10 11 15 13 14 18 16 17 19 20 moto1 mute moto2 16 17 15 33 m f (16 v) c18 88 m f (16 v) c15 3.3 nf (100 v) c17 3.3 nf (100 v) c18 c19 r8 r10 22 m f (35 v) 22 m f (38 v) 47 k w (0.4 w) 100 k w (0.4 w) r7 47 k w (0.6 w) r9 47 k w (0.6 w) audio in r audio in l r6 47 k w (0.4 w) c17 v ssd v ssd v ssd v ssd c25 470 pf (50 v) c26 470 pf (50 v) c27 470 pf (50 v) c28 470 pf (50 v) c33 470 pf (50 v) c32 0.47 m f (50 v) c30 220 m f (50 v) 3.0 v dd 3.3 v dd 3.0 v dd 3.3 v dd earth tza1048 v ssd v ssd v ssd v ssd c20 33 pf (100 v) c21 33 pf (100 v) c23 1 nf (50 v) c24 100 nf (50 v) c22 10 m f (50 v) c8 10 m f (50 v) c6 10 m f (15 v) c7 10 nf (50 v) 18 gnd 19 vb out 20 sl1 21 fo1 22 30 ra1 23 mute 24 25 26 3.3 v fb 27 3.3 v out 1.8 v out 1.65 v out 1.8 v fb moto + moto - v cc slo - slo + b sledge + wh sledge - g motor + y motor - home_sw tray_sw ld mon to cd mechanism (vam220x) d1 d2 r1 r2 bl v cc v cc rado+ foco- rado - v cc foco + rad+ foc- rad - foc + gnd gnd x1 1 x1 2 x1 3 x1 4 x2 5 x2 6 x2 3 x2 4 x2 2 x2 1 x3 1 x3 2 tr3 bc337 3.3 v dd x1 10 x1 9 x1 15 x1 5 x1 12 x1 6 x1 14 x1 8 x1 11 x1 13 x1 7 28 13 12 14 11 10 9 8 7 29 6 5 4 3 2 1 v ssd v ssd tr4 bc337 r15 100 k w (0.4 w) b a c d e f g h j k l m o n p r s fig.40 typical application diagram incorporating a voltage mechanism (continued in fig.41).
2003 oct 01 83 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 handbook, full pagewidth SAA7824hl mbl454 v2 v1 v ddd3 v ssd3 moto2 moto1 sl fo ra v ddd2 dobm v ssd2 29 30 31 32 33 34 35 36 37 38 39 40 72 71 70 69 68 67 66 65 64 63 62 61 bufinr bufoutr bufoutl bufinl bufgnd lkill rkill cdtrdy cdtdata cdtclk cflag v ssd1 sbsy c4 100 nf (50 v) c1 100 nf (50 v) c2 33 m f (16 v) sfsy v ssd to mini micro for playability test to headphone v ssd 3.3 v dd 1.8 v dd sub 58 60 59 55 57 56 52 54 53 49 51 50 46 48 47 43 45 44 42 41 rck status sild mute status tray 5 w rab scl sda reset clk4/12 clk16 sclk wclk data ef scli wcli sdi v ddd1 r12 10 w (0.6 w) c9 100 nf (50 v) scl sda reset cdtclk cdtdata cdtrdy wclk sclk cflag data c8 33 m f (16 v) v ssd 5 v v ssd c11 33 m f (16 v) 10 w (0.6 w) 33 m f (16 v) r10 10 k w 10 m f (50 v) 10 m f (50 v) 10 w (0.6 w) c10 c14 c16 1 2 34 audio l audio r 5 r23 r22 v ssd v ssd v ssd 3.3 v dd v ssd 3.3 v dd c5 100 nf (50 v) r14 10 k w (0.6 w) r16 24 k w (0.6 w) r11 10 w (0.6 w) r4 24 k w (0.6 w) r13 10 k w (0.6 w) r3 24 k w (0.6 w) r2 24 k w (0.6 w) r1 24 k w (0.6 w) v cc in (12 v) v ssd v ssd v ssd v ssd 3.3 v dd tr1 bc337 tr2 bc337 1.8 v dd x4 1 v cc in (5 v) x4 2 x4 3 audio out (r) x4 4 x4 5 audio out (l) x4 6 x5 1 x5 2 x5 3 x5 4 x5 5 x5 6 x5 7 x5 8 x5 9 x5 10 x5 11 x5 12 x6 1 x6 2 x6 3 x6 4 x6 5 x6 6 c36 10 nf (50 v) v ssd v ssd v ssd c37 10 nf (50 v) o bmd d f b b b polb stereo 3.5 m s 5 v audio_r audio_l v ssd b a c d e f g h j k l m o n p r s fig.41 typical application diagram incorporating a voltage mechanism (continued from fig.40).
2003 oct 01 84 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 15 package outline unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec jeita mm 1.6 0.16 0.04 1.5 1.3 0.25 0.27 0.13 0.18 0.12 12.1 11.9 0.5 14.15 13.85 1.45 1.05 7 0 o o 0.15 0.1 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.30 sot315-1 136e15 ms-026 00-01-19 03-02-25 d (1) (1) (1) 12.1 11.9 h d 14.15 13.85 e z 1.45 1.05 d b p e q e a 1 a l p detail x l (a ) 3 b 20 c d h b p e h a 2 v m b d z d a z e e v m a x 1 80 61 60 41 40 21 y pin 1 index w m w m 0 5 10 mm scale lqfp80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm sot315-1
2003 oct 01 85 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 16 soldering 16.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for fine pitch smds. in these situations reflow soldering is recommended. 16.2 re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 220 c for thick/large packages, and below 235 c for small/thin packages. 16.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 16.4 manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
2003 oct 01 86 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 16.5 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales office. 2. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 3. these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 5. wave soldering is suitable for lqfp, tqfp and qfp packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. wave soldering is suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. package (1) soldering method wave reflow (2) bga, lbga, lfbga, sqfp, tfbga, vfbga not suitable suitable hbcc, hbga, hlqfp, hsqfp, hsop, htqfp, htssop, hvqfn, hvson, sms not suitable (3) suitable plcc (4) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (4)(5) suitable ssop, tssop, vso not recommended (6) suitable
2003 oct 01 87 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 17 data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. 3. for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level data sheet status (1) product status (2)(3) definition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn). 18 definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 19 disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2003 oct 01 88 philips semiconductors product speci?cation cd audio decoder, digital servo and ?lterless dac with integrated pre-amp and laser control SAA7824 20 purchase of philips i 2 c components purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
? koninklijke philips electronics n.v. 2003 sca75 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands r04/03/pp 89 date of release: 2003 oct 01 document order number: 9397 750 12009

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